3D NAND Flash Memory Erase Reset Method

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Solution Overview

Problem

Three-dimensional (3D) NAND memory devices face challenges in data retention due to defects and mobile charges generated during erase operations, leading to reduced reliability and increased bit error rates.

Innovation Solution

A method for operating 3D memory devices involves performing an erase operation on a selected memory block while inhibiting the erase operation on unselected blocks and applying a reset voltage on the word lines of unselected blocks to reset them, which includes applying specific voltages to manage the erase and reset processes effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high voltage is applied to erase memory cells, then storage data is removed, but defects and mobile charges are generated in memory films

Engineering Contradiction:

Improvedata retentionVSAvoiddefects and mobile charges

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A reset voltage is applied to word lines before the erase operation to prepare the memory block by removing mobile charges and preventing defect formation during subsequent high-voltage erase, thus preliminarily protecting against harmful effects

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The reset operation converts potentially harmful mobile charges generated during erase into beneficial effects by removing them through a controlled reset voltage application, transforming the harmful byproduct into an opportunity for reliability enhancement

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Productivity

If erase operation is performed on entire memory block, then storage data is removed, but unselected blocks are affected

Engineering Contradiction:

Improveerase operation efficiencyVSAvoiddata retention in unselected blocks

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The reset voltage is selectively applied only to unselected memory blocks during or after the erase operation, providing localized protection to specific blocks that would otherwise be affected by the erase process, thereby maintaining local data retention while preserving overall erase efficiency

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11443813B2Methods for erase and reset in a three-dimensional NAND flash memory

Publication Date: 2022.09.13 YANGTZE MEMORY TECH CO LTD

AI summary

Methods for erasing storage data of a three-dimensional (3D) memory device are presented. The 3D memory device includes a plurality of memory blocks, each memory block having a plurality of memory strings with vertically stacked memory cells. Each memory cell is addressable through a word line and a bit line. The storage data in a selected memory block can be erased by applying an erase voltage on an array common source and applying a first voltage on the word lines of the selected memory block. Word lines of an unselected memory block are floating, i.e., without external bias, during the erasing operation. After the erasing operation, a second voltage is applied on the word lines of entire memory plane to reset the memory cells for improved data retention.