3D NAND Flash Memory for Analog Neural Network Processing
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Solution Overview
Problem
Current neural network processing systems face delays and high power consumption due to the separation of memory from processing circuitry, which is exacerbated by the need for frequent memory access during vector matrix multiplication (VMM) operations.
Innovation Solution
The use of 3D NAND flash memory as a processing-in-memory (PIM) backbone for performing VMM in analog neural networks, where the resistance of 3D NAND flash cells represents weights and a controller manages voltage applications to perform current integration for efficient computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory and processing circuitry are separated, then device architecture is simplified and manufacturing is easier, but processing delays increase and power consumption rises due to frequent memory access during VMM operations
Solution Approach 1:
The patent combines memory and processing circuitry into a unified structure where 3D NAND flash memory cells directly perform VMM operations. The memory cells are configured with control gates that receive input voltages, and their conductance values represent weights, enabling multiplication and accumulation operations to occur within the memory array itself rather than separating memory from processing units.
Solution Approach 2:
The 3D NAND flash memory cells serve multiple functions: they store data (memory function) and simultaneously perform computational operations (processing function). The same physical structure is used for both memory storage and analog VMM computation, eliminating the need for separate processing circuitry and reducing data transfer overhead.
2Device complexity
If memory and processing circuitry are separated, then device design is simpler, but power consumption increases due to frequent memory access during VMM operations
Solution Approach 1:
The patent merges memory and processing functions into the same physical substrate (3D NAND flash memory array), allowing VMM operations to be performed in-place without data movement between separate memory and processing units. This eliminates the energy overhead associated with data transfer and enables lower power consumption for neural network inference operations.
Solution Approach 2:
The patent replaces traditional digital processing mechanisms with analog computation using the electrical properties (conductance) of memory cells. By utilizing the natural physical properties of the memory cells rather than requiring complex digital processing circuits, the system achieves efficient computation with reduced power consumption.
3Productivity
If 3D NAND flash memory is used for VMM operations, then processing speed and efficiency improve, but manufacturing precision requirements increase due to analog weight representation
Solution Approach 1:
The patent changes the operational parameters of 3D NAND flash memory from traditional digital read/write operations to analog conductance-based computation. By utilizing the continuous range of conductance values that can be achieved through controlled voltage application and charge trapping, the system represents weights as analog values, enabling high-speed VMM operations while leveraging the existing variability in memory cell characteristics rather than requiring tight manufacturing tolerances.
Solution Approach 2:
The patent exploits the porous trapping layer structure in 3D NAND flash memory, which allows controlled charge trapping and results in a distribution of conductance values. This inherent variability, rather than being a defect, is utilized to represent different weight values in the neural network, reducing the need for precise manufacturing control while enabling analog computation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes delays and power consumption by integrating processing with memory, enabling fast and efficient VMM operations within the neural network, suitable for various machine learning workloads without requiring modifications to existing arrays.
Implementation Method 1
a resistance of each 3D NAND flash cell in the plurality of blocks represents a weight in the ANN
Implementation Method 2
The controller, during a read operation, applies a read voltage, via the first word line, to control gates of the 3D NAND flash cells in the first block such that a first current flows to the first bit line
Implementation Method 3
an integrator connected to the bit line
Data Source
AI summary
An apparatus performs vector matrix multiplication (VMM) for an analog neural network (ANN). The apparatus includes a column of NAND flash cells in series, where each NAND flash cell includes a control gate; a bit line connected to the column of NAND flash cells, where a current drawn from the NAND flash cells flows to the bit line; an integrator connected to the bit line; and a controller having programmed instructions to control the column of NAND flash cells by setting the voltage of the control gate of each NAND flash cell.