3D NAND Flash Multi-Phase Programming for Coupling

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Solution Overview

Problem

In 3D NAND flash memory arrays, cell-to-cell coupling effects increase due to the vertical structure, leading to reliability issues and data retention problems, especially as technology nodes shrink, making it difficult to maintain storage density and reliability.

Innovation Solution

Implementing a multi-phase programming scheme that controls the order of programming different cells, pages, and blocks, and using decoupling methods during read operations to mitigate coupling effects, including specific programming orders and read strategies to reduce the impact of neighboring cells on threshold voltage measurements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multi-level programming is implemented to increase storage density, then storage capacity is improved, but cell-to-cell coupling effects worsen due to vertical structure interference

Engineering Contradiction:
Improvestorage densityVSAvoiddata retention
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the programming process into multiple phases (e.g., MSB programming, CSB programming, LSB programming) and divides the memory array into different blocks that are programmed in a specific sequence. This segmentation reduces cell-to-cell coupling effects by controlling which blocks are programmed together, thereby maintaining data retention reliability while achieving multi-level storage density.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If technology node is shrunk to increase storage capacity, then storage density is improved, but cell-to-cell coupling effects worsen due to reduced spacing between cells

Engineering Contradiction:
Improvestorage capacityVSAvoidcoupling effects
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent applies different programming strategies to different locations within the memory array. Edge blocks (those at the periphery) are programmed differently from inner blocks to account for varying coupling effects. This local quality approach allows the system to maintain high storage capacity at shrunk technology nodes while compensating for location-specific coupling interference through adaptive programming sequences and threshold voltage adjustments.

Inventive Principle:
Principle #3Local quality

3Productivity

If programming speed is increased by overlapping operations, then productivity is improved, but measurement precision worsens due to interference from neighboring cells

Engineering Contradiction:
Improveprogramming speedVSAvoidthreshold voltage measurement
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent performs preliminary read operations and threshold voltage measurements before final programming decisions are made. By conducting preliminary actions to assess the current state of cells and predict coupling effects, the system can adjust programming parameters in advance, thereby maintaining measurement precision even when operating at high programming speeds with overlapping operations.

Inventive Principle:
Principle #10Preliminary action

4Quantity of substance

If more bits per cell are stored using multiple charge levels, then storage density is improved, but reliability worsens due to lobe overlap and retention effects

Engineering Contradiction:
Improvebits per cellVSAvoiddata retention
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent dynamically adjusts programming parameters such as pulse voltage levels, pulse durations, and programming sequences based on the desired charge level and the current state of the memory cells. By changing these parameters adaptively during multi-level programming, the system can create well-separated voltage lobes for each bit level, reducing overlap and improving data retention reliability while maintaining high bits-per-cell capacity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9536612B1Digital signaling processing for three dimensional flash memory arrays
Publication Date: 2017.01.03 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9536612B1 patent drawing
  • US9536612B1 patent drawing
  • US9536612B1 patent drawing

AI summary

A method for multilevel programming flash memory cells of a three dimensional array of flash memory cells, the method may include receiving or determining a multiple phase programming scheme that is responsive to coupling between flash memory cells of the three dimensional array; and programming data to multiple flash memory cells of the three dimensional array in response to the multiple phase programming scheme. The multiple phase programming scheme determine a manner in which multiple programming levels are applied. At least two programming levels of the multiple programming levels correspond to bits of different significance.