3D NAND Flash Memory Voltage Control for Charge Trapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensionally stacked NAND flash memory devices face challenges in maintaining operational reliability due to excessive electric charge trapping in charge accumulation layers between adjacent word lines, leading to deteriorated retention characteristics and increased complexity in controlling numerous interconnections.
Innovation Solution
The semiconductor memory device employs a programming method where a high voltage is applied to a selected word line and an intermediate voltage, VPASSA, is applied to unselected word lines, with VPASSA being stepped down during repeated programming operations to manage the composite electric field and localize charge injection, while sharing word lines across memory groups to reduce decoder size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally stacked to increase storage capacity, then the storage density is improved, but excessive electric charge trapping occurs in charge accumulation layers between adjacent word lines, deteriorating retention characteristics
Solution Approach 1:
The patent applies different voltage levels to different word lines based on their selection status: selected word lines receive high voltage for programming, unselected word lines adjacent to selected lines receive intermediate voltage to suppress charge trapping, and other unselected word lines receive low voltage. This localized voltage differentiation resolves the charge trapping issue while maintaining 3D stacking benefits
Solution Approach 2:
The patent dynamically changes voltage parameters during programming operations by stepping up the high voltage applied to selected word lines and stepping down the intermediate voltage applied to unselected word lines. This parameter modulation prevents excessive electric field buildup and charge trapping in charge accumulation layers, thereby improving retention characteristics while maintaining storage capacity
2Quantity of substance
If numerous word lines are used in three-dimensional stacking to increase memory density, then the storage capacity is improved, but the complexity of controlling interconnections increases
Solution Approach 1:
The patent segments word lines into three distinct groups based on their spatial and functional characteristics: selected word lines (receiving high voltage), unselected word lines adjacent to selected lines (receiving intermediate voltage), and other unselected word lines (receiving low voltage). This segmentation simplifies control logic by assigning specific voltage roles to different word line categories, reducing the complexity of managing numerous interconnections in 3D stacked memory
3Productivity
If high voltage is continuously applied to selected word lines during repeated programming operations, then data writing speed is improved, but excessive electric field increase causes charge trapping in charge accumulation layers
Solution Approach 1:
The patent implements dynamic voltage adjustment during repeated programming operations by stepping up the high voltage applied to selected word lines to maintain programming effectiveness, while simultaneously stepping down the intermediate voltage applied to unselected word lines to prevent excessive electric field buildup. This dynamic control maintains data writing speed while preventing charge trapping and improving operational reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents excessive electric charge trapping, improves data retention, and enhances operational reliability by localizing charge injection and reducing the complexity of row decoders through voltage management and interconnection sharing.
Implementation Method 1
a first voltage is applied to a selected word line, a second voltage to first unselected word lines, and a third voltage to second unselected word lines
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The memory cells are stacked above a semiconductor substrate, and each includes a charge accumulation layer and control gate. The word lines are coupled to the control gates. The driver circuit repeats a programming operation to write data in a memory cell coupled to a selected word line. In the programming operation, a first voltage is applied to the selected word line, a second voltage to a first unselected word line, and a third voltage to a second unselected word line. The control circuit steps up the first voltage and steps down the second voltage in repeating the programming.