3D NAND Memory Cell Flat Trap Base Profile
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
3D NAND memory cells face challenges with pillar etch maximum critical dimension (CD) issues, leading to problems such as taper, notching, and necking, which affect the uniformity and reliability of cell films and electrical characteristics.
Innovation Solution
The solution involves relaxing the pillar etch max CD and adjusting the control gate recess to maintain overall control gate size, using a process flow that includes atomic layer deposition oxide and selective polysilicon deposition to form tunnel oxide, resulting in improved taper and necking, and reducing waviness and roughness in the vertical channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pillar etch maximum critical dimension is relaxed to improve manufacturing ease, then pillar etch uniformity and cell film uniformity improve, but the control gate size may become insufficient
Solution Approach 1:
The control gate structure is segmented into multiple components: the control gate electrode itself, the trap base, and the tunnel oxide layer. This segmentation allows each component to be optimized independently - the control gate electrode can be sized for electrical performance while the trap base extends to provide the necessary structural profile for uniform cell films
Solution Approach 2:
The trap base extends in the vertical dimension beyond the control gate electrode, creating a stepped profile. This vertical extension allows the control gate to maintain its horizontal dimensions for electrical performance while the trap base provides the extended vertical profile needed for uniform cell film formation and relaxed etch constraints
2Manufacturing precision
If the trap base profile is made flat to improve cell film uniformity, then waviness and roughness in the vertical channel are reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The trap base is formed preliminarily before the control gate electrode is deposited. By establishing the flat trap base profile first, subsequent layers (tunnel oxide, control gate electrode) can be deposited conformally, ensuring uniform cell film formation without requiring complex in-situ profile adjustments during later processing steps
Solution Approach 2:
The trap base acts as an intermediary structure between the vertical channel and the control gate electrode. It provides a flat, stable foundation that mediates the interface between these components, ensuring uniform cell film formation while simplifying the overall manufacturing process by decoupling the profile control function from the control gate electrode deposition
3Reliability
If the control gate recess is adjusted to maintain control gate size, then electrical characteristics improve, but the tunnel oxide thickness control becomes more difficult
Solution Approach 1:
The recess geometry is optimized locally with specific dimensions and angles that enable conformal tunnel oxide deposition. The recess depth, width, and corner radii are carefully controlled to ensure uniform tunnel oxide thickness throughout the structure, while still allowing the control gate electrode to achieve its target dimensions for optimal electrical characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances pillar etch uniformity, cell film uniformity, and reliability, improving electrical characteristics and widening the cell formation margin to prevent pinch-off or punch under etch, while maintaining suitable tunnel oxide thickness and trap base shape.
Implementation Method 1
using a process flow that includes atomic layer deposition oxide to form tunnel oxide
Implementation Method 2
selective polysilicon deposition to form tunnel oxide
Data Source
AI summary
An embodiment of an apparatus may include a substrate with alternated layers of conductor material and insulator material, a vertical channel through at least four of the alternated layers of the substrate, where an edge of the layers of insulator material abuts an edge of the vertical channel, and a memory cell on the vertical channel disposed in a layer of conductor material between two layers of the insulator material, where the memory cell comprises a control gate disposed in a recess of the layer of conductor material between the two layers of the insulator material, a trap base disposed in the recess between the control gate and the edge of the vertical channel, and tunnel oxide material that covers the trap base and extends into the vertical channel outside of the recess and beyond the edge of the two layers of insulator material. Other embodiments are disclosed and claimed.