3D-NAND Floating Gate Air Gaps Eliminate Horizontal Charge Trapping
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Solution Overview
Problem
Three-dimensional (3D)-NAND Flash memory devices face issues with charge trapping in the horizontal ONO charge blocking material, which degrades cell program-erase cycling and alters threshold voltage, compromising the controllability and reliability of memory cells.
Innovation Solution
The semiconductor structure is designed with a stack of alternating tier dielectric and control gate materials, where the charge blocking material is vertically positioned between floating gates and control gates, and air gaps or conductive materials are used horizontally between floating gates and tier dielectric materials to eliminate horizontal charge trapping, thereby reducing undesirable charge traps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge blocking material (e.g., ONO material) is used horizontally between floating gates and tier dielectric materials, then charge storage capability is improved, but charge trapping occurs which degrades program-erase cycling and alters threshold voltage
Solution Approach 1:
The patent removes the charge blocking material from the horizontal region between floating gates and tier dielectric materials, extracting only the necessary charge blocking function from problematic locations while preserving it where needed for charge storage
Solution Approach 2:
The patent applies charge blocking material selectively in specific locations (vertically between floating gates and control gates) while omitting it from other locations (horizontally between floating gates and tier dielectric materials), creating local quality variations to achieve different functional requirements in different regions
2Reliability
If charge blocking material is positioned horizontally between floating gates and tier dielectric materials, then charge trapping is reduced, but threshold voltage control is compromised due to charge migration
Solution Approach 1:
The patent extracts the charge blocking material from horizontal positions where it would allow charge migration paths, eliminating the source of charge migration while maintaining charge blocking functionality in vertical positions
Solution Approach 2:
The patent introduces air gaps or dielectric materials as intermediary structures between floating gates and tier dielectric materials, providing physical separation that prevents charge migration while maintaining electrical isolation
3Quantity of substance
If memory density is increased through 3D stacking, then storage capacity is improved, but critical dimensions are degraded due to charge trapping in charge blocking material
Solution Approach 1:
The patent removes charge blocking material from horizontal regions to eliminate charge trapping that would compromise critical dimensions, enabling continued scaling and increasing memory density without degradation of manufacturing precision
Solution Approach 2:
The patent repositions charge blocking material from horizontal to vertical orientations in the stacked structure, utilizing the third dimension to maintain charge blocking functionality while eliminating the problematic horizontal charge trapping paths that limit scaling
Data Source
AI summary
Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods.