Three-Dimensional NAND Gate Layer End Part Thickness

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Solution Overview

Problem

Three-dimensional NAND flash memory devices face challenges in the integration and fabrication process, particularly in forming contact openings with sufficient depth without etching through the gate layer, which affects the yield and reliability of the memory device.

Innovation Solution

A stacked structure with alternating conductive and insulating layers is formed, including a staircase region with support pillars to prevent collapse during etching, and an end part with increased thickness is created to prevent etching through the gate layer, integrated with existing processes to enhance the fabrication yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If contact openings with greater depths are formed, then the contact can reach deeper structures, but the gate layer under contact openings with smaller depths may be etched through

Engineering Contradiction:
Improvedepth of contact openingVSAvoidintegrity of gate layer
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The patent applies local quality by forming an end part of the gate electrode with increased thickness specifically at regions where contact openings are to be formed. This localized thickening ensures that when contact openings of greater depth are etched, the etching process does not penetrate through the gate layer, thereby maintaining gate layer integrity while enabling deeper contact formation.

Inventive Principle:
Principle #3Local quality

2Reliability

If the thickness of the gate electrode is uniformly increased, then the gate layer integrity is improved, but the fabrication process complexity increases

Engineering Contradiction:
Improveintegrity of gate layerVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of uniformly increasing the gate electrode thickness throughout the entire structure, the patent implements local quality by selectively forming a thicker end part only at specific locations where contact openings will be formed. This approach maintains gate layer integrity where needed while avoiding unnecessary complexity in regions where such thickening is not required.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The gate electrode is segmented into two distinct parts: a main body with standard thickness and an end part with increased thickness. This segmentation allows the structure to meet different functional requirements in different regions, simplifying the overall fabrication process compared to a uniform thickening approach.

Inventive Principle:
Principle #1Segmentation

3Productivity

If the end part thickness is increased, then the process window for forming contact openings is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
Improveprocess windowVSAvoidthickness control precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent utilizes parameter changes by forming the end part with a specifically increased thickness parameter compared to the main body of the gate electrode. This parameter modification (thickness increase) directly expands the process window, providing greater tolerance variations during the contact opening formation process while maintaining sufficient gate layer protection.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11521898B2Three-dimensional NAND flash memory device and method of fabricating the same
Publication Date: 2022.12.06 MACRONIX INTERNATIONAL CO LTD
  • US11521898B2 patent drawing
  • US11521898B2 patent drawing
  • US11521898B2 patent drawing

AI summary

A memory device is provided. The memory device includes a substrate, a stacked structure, and a contact. The substrate includes a memory array region and a staircase region. The stacked structure is located on the substrate in the memory array region and the staircase region. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers alternately stacked on each other. Each of the plurality of conductive layers includes a main body and an end part. The main body is located in the memory array region and extends to the staircase region. The end part is connected to the main body and is located in the staircase region. A thickness of the end part is greater than a thickness of the main body. The contact lands on and is connected to the end part.