3D NAND Gate Line Isolation for Lower Capacitive Coupling

The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked memory architecture. Multiple layers of memory cells are stacked vertically on the substrate, with each layer containing memory cells arranged in strings. This dimensional change allows storage density to increase significantly while maintaining larger individual cell dimensions that avoid the process limitations and reliability issues associated with extreme planar scaling.

The patent introduces an isolation layer as an intermediary material disposed within the gate line slit between adjacent sub-storage units. This isolation layer acts as a barrier that prevents capacitive coupling effects between the sub-storage units while allowing the GLS structure to maintain its function of dividing the memory block into independently accessible sub-storage units, thereby improving read and program speeds without the harmful capacitive coupling.

The isolation layer serves multiple functions simultaneously: it provides electrical isolation between gate electrodes in different sub-storage units, acts as a barrier to prevent capacitive coupling effects, and facilitates the fabrication process by enabling subsequent removal of substrate and memory film portions. This multi-functionality reduces the need for additional specialized layers or processes, thereby managing fabrication complexity while achieving reliable electrical isolation.

The patent performs preliminary actions by first forming the isolation layer on the GLS opening sidewall and then removing portions of the substrate and memory film in a controlled sequence. The isolation layer is prepared in advance to protect the channel layer during subsequent processing steps. This preliminary preparation ensures that when the substrate and memory film portions are removed to expose the channel layer for forming array common source contacts, the channel layer remains undamaged and properly accessible.