3D NAND Memory Gate Line Slit Formation via Deck Segmentation
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Solution Overview
Problem
As critical dimensions of devices in integrated circuits shrink, 3D NAND memory devices face challenges in forming gate line slits (GLS) through multiple stacking layers, leading to issues like incomplete openings, twisted profiles, and mechanical stress-induced damage due to the complexity of etching processes.
Innovation Solution
The implementation of a multi-deck configuration where GLSs are formed deck by deck, allowing for separate etching of per-deck GLSs with staggered sidewalls and varying distribution patterns to mitigate stress and improve controllability, reducing the etch depth and processing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single etching process is used to form GLS through all stacking layers, then the etching process is simple, but the GLS openings become incomplete and twisted due to excessive etch depth
Solution Approach 1:
The patent divides the stacking layers into multiple decks and forms GLS openings in each deck separately using independent etching processes. This segmentation approach allows each etching process to operate at a manageable depth within a single deck, preventing the twisting and incompleteness that occur when etching through all stacking layers at once.
2Quantity of substance
If GLS are formed through multiple stacking layers, then the device achieves high storage capacity, but mechanical stress causes damage to the GLS structure
Solution Approach 1:
By segmenting the stacking layers into decks with separate GLS formation processes, the patent reduces the mechanical stress accumulation that would otherwise occur in a single deep etching process. Each deck's GLS is formed independently, minimizing stress-induced damage while maintaining the high storage capacity enabled by multiple stacking layers.
Solution Approach 2:
The patent applies different etching processes to different decks, allowing local optimization of GLS formation in each deck. This local quality approach enables tailored etching parameters for each deck, improving GLS structural integrity while maintaining overall device functionality and storage capacity.
3Productivity
If a single etching process is used for all decks, then the manufacturing process is efficient, but the GLS profile becomes twisted and mechanical stress increases
Solution Approach 1:
The patent segments the manufacturing process by forming GLS openings in each deck separately rather than using a single process for all decks. This segmentation maintains productivity by processing decks in parallel while ensuring each GLS opening receives optimized etching treatment that prevents profile twisting.
Solution Approach 2:
The patent employs different etching parameters for different decks, allowing optimization of each deck's GLS formation. By changing parameters such as etching depth, width, and conditions for each deck, the patent maintains straight GLS profiles while preserving manufacturing efficiency through parallel processing.
4Length of stationary object
If deep etching is used to form GLS through all stacking layers, then the GLS spans the entire device height, but the etching process becomes complex and stress-induced damage increases
Solution Approach 1:
The patent segments the vertical span of GLS formation into multiple decks, with each deck having its own etching process. This approach achieves the required vertical span across the entire device while avoiding the complexity and stress damage associated with a single deep etching process through all stacking layers.
Data Source
AI summary
A semiconductor device includes N number of decks. Each deck includes alternating word line layers and insulating layers. Each deck includes two first gate line slit (GLS) structures and a second GLS structure positioned between the two first GLS structures. The two first GLS structures and the second GLS structures each extend in an X-Z plane and cut through the word line layers and the insulating layers of the respective deck. At least one second GLS structure of at least one deck in the N umber of decks includes multiple sub-GLS structures. The multiple sub-GLS structures are separate from each other.