3D NAND Source Select Gate Structure for Threshold Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 2D NAND memory devices face challenges in increasing storage capacity within the same semiconductor size, particularly in fabricating staircase structures, channel holes, gate line slits, and oxide-nitride-oxide deposition in increased layers, which affects reliability and durability due to frequent electric charge trimming.
Innovation Solution
The introduction of a 3D memory device architecture with a source select gate line formed like a CMOS structure, using a sacrificial layer as an etch stop to precisely control the etch process during channel hole and gate line slit formation, and incorporating a doped semiconductor layer to improve threshold voltage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar process technology is improved to scale devices to smaller sizes, then device density is improved, but fabrication cost and process difficulty increase significantly as feature sizes approach lower limits
Solution Approach 1:
The patent transitions from planar (2D) device architecture to three-dimensional (3D) vertically-stacked architecture. Multiple memory layers are stacked vertically with interleaved bit lines extending between layers, enabling continued density scaling without further reducing lateral feature sizes and their associated fabrication challenges
2Quantity of substance
If 3D semiconductor device architecture is used to address density limitations, then storage capacity is improved, but source select gate line structure issues affect reliability and durability
Solution Approach 1:
An intermediate layer is introduced between the source select gate line and the channel structure. This intermediate layer acts as a protective mediator that prevents direct harmful interactions, thereby improving the reliability and durability of the source select gate line while maintaining the 3D vertical architecture for high storage capacity
3Ease of manufacture
If conventional source select gate line structures are used in 3D devices, then manufacturing is simplified, but threshold voltage stability deteriorates
Solution Approach 1:
The source select gate line structure is enhanced with composite material layers including high-k dielectric materials and tailored doping profiles. This composite structure maintains manufacturing feasibility while significantly improving threshold voltage stability through the combined properties of different materials and controlled electrical characteristics
Data Source
AI summary
Three-dimensional (3D) memory devices and methods for forming the same are disclosed. The 3D memory device includes a doped semiconductor layer, a source select gate line disposed on the doped semiconductor layer, a stack structure including interleaved conductive layers and dielectric layers formed on the source select gate line, and a channel structure extending through the stack structure and the source select gate line and in contact with the doped semiconductor layer. The channel structure includes a semiconductor channel and a memory film. The source select gate line is in contact with the semiconductor channel.