3D NAND Gate Stack Structure for Higher Storage Density
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Solution Overview
Problem
Current semiconductor devices face limitations in increasing data storage capacity, particularly in achieving high-capacity storage in a compact form, as traditional two-dimensional memory cell arrangements are inefficient in terms of integration and storage density.
Innovation Solution
The semiconductor device incorporates a three-dimensional structure with a substrate, circuit elements, and interconnection lines, featuring stacked gate electrodes, channel structures, stud structures, and gate dielectric layers to enhance integration and storage capacity, including a plate layer with vertically spaced gate electrodes and upper isolation regions to optimize data storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional memory cell arrangements are used, then device structure is simple, but data storage capacity and integration degree are limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked structure, where multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) are stacked vertically. This dimensional change enables significantly increased storage capacity by utilizing vertical space, allowing multiple memory layers to be integrated within the same footprint area.
2Quantity of substance
If three-dimensional stacked structure is implemented, then data storage capacity increases, but device structure and manufacturing complexity increase
Solution Approach 1:
The three-dimensional structure is segmented into distinct functional layers: first gate electrode with first channel structure, second gate electrode with second channel structure, and third gate electrode with third channel structure. Each layer can be independently designed and manufactured, which modularizes the complex three-dimensional structure and facilitates systematic fabrication processes.
Solution Approach 2:
Multiple gate electrodes and channel structures are nested vertically within each other, forming a compact stacked configuration. The first, second, and third gate electrodes are positioned at different vertical levels with corresponding channel structures, creating a nested arrangement that maximizes space utilization while maintaining structural organization.
3Quantity of substance
If three-dimensional stacked structure is implemented, then storage capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
Different regions of the device exhibit different structural characteristics optimized for their specific functions. The gate electrodes and channel structures are locally configured with precise dimensional control in critical areas (such as gate-channel interfaces), while other regions allow for manufacturing tolerances. This localized precision approach maintains alignment requirements only where functionally critical.
Data Source
AI summary
A semiconductor device comprising; a first semiconductor structure including a substrate, circuit elements on the substrate, and circuit interconnection lines on the circuit elements; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes, a plate layer, a plurality of gate electrodes spaced apart from each other and stacked on the plate layer in a first direction, perpendicular to an upper surface of the plate layer, the gate electrodes including a lower select gate electrode, memory gate electrodes, and an upper select gate electrode sequentially stacked, channel structures passing through the lower select gate electrode and the memory gate electrodes and extending in the first direction, stud structures passing through the upper select gate electrode and respectively connected to the channel structures.