3D NAND Memory Gate Uniformity via Mandrel Etching
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Solution Overview
Problem
The existing methods for fabricating 3D vertical-channel non-volatile memory devices result in tapered trenches and varying gate resistances due to the etching process, leading to deteriorated operation performance of memory cells.
Innovation Solution
A method involving a multi-layers stack with insulating and conductive layers, where a dielectric layer with extending parts is used to isolate conductive layers from contact plugs, and controlled etching processes ensure uniform gate sizes and resistance across different levels, preventing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a standard etching process is used to form trenches in the multi-layers stack, then the trenches can be formed efficiently, but the trenches will have a tapered cross-sectional profile resulting in non-uniform gate sizes and varying resistance
Solution Approach 1:
A mandrel layer is formed at the bottom of the trench before the conductive layers are deposited. This mandrel structure serves as a preliminary form that guides the deposition process and ensures uniform gate formation. The mandrel is removed after the conductive layers are formed, leaving behind uniformly sized gates despite the tapered trench profile.
Solution Approach 2:
The etching process parameters are optimized to control the trench profile while maintaining productivity. By adjusting etching conditions, the trench shape is controlled to work effectively with the mandrel-based uniform gate formation approach, resolving the contradiction between etching efficiency and gate uniformity.
2Ease of manufacture
If the conductive layers are formed to fill the tapered trenches, then the gates at different levels will have different lateral sizes, but this leads to different resistance values and deteriorated operation performance
Solution Approach 1:
The mandrel layer is deposited beforehand to establish a uniform base structure. Subsequent conductive layers are deposited conformally over the mandrel, ensuring uniform gate dimensions. The mandrel is then removed, leaving uniformly sized gates with consistent resistance values, thus maintaining both ease of manufacture and operational reliability.
Solution Approach 2:
The mandrel layer acts as an intermediary structure during the gate formation process. It temporarily occupies the trench space and guides the conformal deposition of conductive materials, ensuring uniform gate formation. After serving its purpose, the mandrel is removed, having enabled uniform gate creation without complicating the overall manufacturing process.
3Ease of operation
If the contact plug is formed to pass through the multi-layers stack, then electrical contact is established, but current leakage may occur between the contact plug and conductive layers
Solution Approach 1:
An insulating layer is introduced as an intermediary between the contact plug and the conductive layers. This insulating layer prevents direct electrical contact that would cause current leakage, while still allowing the contact plug to pass through the multi-layers stack and establish proper electrical connections at the intended contact points.
Solution Approach 2:
The insulating layer is strategically positioned only where needed - between the contact plug and conductive layers - to prevent current leakage. The local application of this insulating material ensures that electrical isolation is provided exactly where required, while maintaining proper electrical connectivity elsewhere in the structure.
Data Source
AI summary
A memory device includes memory includes a multi-layers stack includes a plurality of insulating layers and a plurality conductive layers alternatively stacked on a semiconductor device, a plurality of memory cells formed on the conductive layers, a contact plug passing through the insulating layers and the conductive layers, and a dielectric layer including a plurality of extending parts each of which is inserted between each adjacent two ones of the insulating layers to isolate the conductive layer from the contact plug, wherein any one of the extending parts that has a shorter distance departed from the semiconductor substrate has a size substantially greater than a size of the others that has a longer distance departed from the semiconductor substrate.