3D NAND Sub-Block Pre-Charge Using GIDL for Program Disturb Control
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Solution Overview
Problem
As memory structures increase in density, programming and maintaining data integrity becomes challenging due to issues like charge leakage, read and write disturbs, and erase disturbs in non-volatile memory cells, particularly in three-dimensional NAND arrays, leading to data degradation and unreadable states.
Innovation Solution
A memory apparatus and method that applies programming pulses followed by verification pulses, ramps voltages during pre-charge operations, and generates gate-induced drain leakage current to pre-charge channels, addressing sub-block level programming difficulties and maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory structures increase in density to improve storage capacity, then storage capacity is improved, but charge leakage and data integrity issues worsen
Solution Approach 1:
The patent applies preliminary pre-charge operations to memory strings before programming operations. By pre-charging the channel to a positive voltage state beforehand, the memory cells are prepared in advance to resist charge leakage and programming disturbances, thereby maintaining data integrity in high-density structures
Solution Approach 2:
The patent implements preliminary anti-action by applying pre-charge voltages that counteract the harmful effects of charge leakage and programming disturbances before they can degrade data integrity. This preventive approach addresses the reliability issues that arise from increased density
2Productivity
If programming pulses are applied to selected word lines to program memory cells, then programming capability is improved, but program disturb to unselected cells worsens
Solution Approach 1:
The patent applies local quality by implementing sub-block level pre-charge operations that selectively target specific regions of the memory array. By applying pre-charge voltages only to unselected sub-blocks while programming selected sub-blocks, the patent localizes the protective action to where it is most needed, preventing program disturb without affecting overall programming capability
Solution Approach 2:
The patent segments the memory array into multiple sub-blocks and applies different voltage conditions to each segment during programming operations. This segmentation allows independent control of programming and pre-charge operations in different regions, enabling high-speed programming of selected blocks while protecting unselected blocks from disturb effects
3Reliability
If pre-charge voltage is applied to all strings to prevent program disturb, then data integrity is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by implementing selective pre-charge operations that target only unselected sub-blocks or strings that require protection from program disturb. By applying pre-charge voltages locally rather than globally to the entire memory array, the patent reduces unnecessary power consumption while maintaining data integrity in protected regions
Solution Approach 2:
The patent implements partial action by applying pre-charge operations to only the extent necessary to prevent program disturb in unselected regions. Rather than pre-charging all strings continuously, the patent applies pre-charge selectively and temporarily only where needed, optimizing the balance between reliability and power consumption
4Productivity
If multiple sub-blocks are programmed simultaneously to improve throughput, then productivity is improved, but interference between sub-blocks worsens
Solution Approach 1:
The patent segments the memory array into multiple independently controllable sub-blocks that can be programmed simultaneously. By dividing the array into discrete segments with independent word line and bit line control, the patent enables parallel programming operations in selected sub-blocks while applying pre-charge protection to unselected sub-blocks, thereby maintaining high throughput while minimizing interference
Solution Approach 2:
The patent implements dynamic voltage control that adapts the pre-charge and programming voltages based on the operational state of different sub-blocks. During simultaneous programming operations, the system dynamically adjusts voltage levels to selected and unselected sub-blocks, enabling coordinated operation that maximizes throughput while preventing interference between adjacent sub-blocks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances data retention and integrity by managing program and erase disturbs, ensuring reliable operation of non-volatile memory systems, particularly in multi-tier structures.
Implementation Method 1
ramping an assist voltage applied to a pre-charge assist portion of the memory apparatus down to a gate-induced leakage voltage to generate gate-induced drain leakage current in the strings and pre-charge the channel of at least some of the strings during the pre-charge operation
Data Source
AI summary
An apparatus includes memory cells connected to word lines and disposed in strings each defining a channel and coupled to bit lines and a source line. The memory cells are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply programming pulses followed by verification pulses of program verify voltages associated with the data states to the word lines during a program operation. The control means ramps a selected word line voltage applied to the word lines from one of the program verify voltages to approximately zero while ramping voltages applied to the bit lines and the source line to a high supply voltage during a pre-charge operation. The control means ramps an assist voltage applied to a pre-charge assist portion of the memory apparatus to generate gate-induced drain leakage current in the strings and pre-charge the channel during the pre-charge operation.