3D NAND Multi-Deck Gate Line Slit Etching for Sidewall Control
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Solution Overview
Problem
As critical dimensions of devices in integrated circuits shrink, forming a gate line slit (GLS) through multiple stacking layers in 3D NAND memory devices becomes increasingly challenging, often resulting in incomplete openings and twisted or notched sidewalls due to the difficulty of etching through numerous layers.
Innovation Solution
Implementing a multi-deck configuration where GLSs are formed deck by deck using separate etch processes, allowing for the formation of sub-GLSs through each deck, reducing etch depth and improving control over GLS shapes, and merging the formation of GLSs and channel structures to share processing costs and lithography masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single etch process is used to form GLS through multiple stacking layers, then the process is simpler and faster, but the etching completeness and sidewall quality deteriorate due to excessive etch depth
Solution Approach 1:
The patent divides the single deep etch process into multiple sequential etch processes, with each process targeting a specific deck (portion of stacking layers). This segmentation reduces the etch depth for each individual process, enabling complete and high-quality GLS formation without the drawbacks of excessive single-process etching depth
Solution Approach 2:
The patent performs preliminary formation of GLS in the first deck before forming subsequent decks. This preliminary action establishes a foundation that guides and supports the etching of remaining decks, ensuring structural integrity and etching completeness throughout the multi-deck structure
2Manufacturing precision
If GLS formation is performed separately for each deck, then the etching control and GLS shape quality improve, but the process complexity and number of steps increase
Solution Approach 1:
The patent merges the formation of GLS and channel structures into integrated processes for each deck. By combining these operations, the patent reduces the total number of separate process steps while maintaining the benefits of deck-by-deck etching control and GLS shape quality
Solution Approach 2:
The patent segments the overall GLS formation into multiple etch processes corresponding to different decks, with each process optimized for its specific depth range. This segmentation improves etching control and GLS shape quality while managing process complexity through systematic organization
3Length of stationary object
If deep etching through numerous layers is performed, then the GLS spans the entire structure, but the risk of structural damage and sidewall defects increases
Solution Approach 1:
The patent segments the deep etching operation into multiple shallower etching steps, each performed on a specific deck. This segmentation reduces the cumulative stress and heat exposure on the structure, minimizing the risk of structural damage and sidewall defects while achieving the required GLS depth
Solution Approach 2:
The patent performs preliminary GLS formation in the first deck to establish a structural foundation before proceeding with subsequent decks. This preliminary action creates a support structure that reduces stress on remaining layers during etching, thereby improving overall structural integrity
Data Source
AI summary
A semiconductor device includes Number of decks that are stacked up in a Z direction and extend in parallel with an X-Y plane. N is an integer greater than 1. Each deck includes alternating word line layers and insulating layers. The N number of decks includes a first deck and a second deck adjacent to the first deck. A multi-deck gate line slit (GLS) structure extends in an X-Z plane and cuts through the word line layers and the insulating layers of the N number of decks. The multi-deck GLS structure has a first sidewall in the first deck, a second sidewall in the second deck, and a third sidewall at a border between the first deck and the second deck. The third sidewall connects the first sidewall and the second sidewall.