3D NAND Ground Select Line Segmentation for Vpass Disturb Reduction
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Solution Overview
Problem
3D memory structures face challenges in increasing bit density while minimizing the negative impacts on power consumption and device operation due to Vpass disturb and process complexities associated with deep hole etching and increased number of select lines.
Innovation Solution
The solution involves varying the number of ground select lines per block to trade off density in the bit line direction for reduced Vpass disturb, with a greater number of ground select lines underlying each word select line, and using arrangements like parallelogram and twisted arrays of pillars to increase bit line density and reduce the number of string select lines, thereby decreasing unit cell capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the number of ground select lines is increased to reduce Vpass disturb, then power consumption and Vpass disturb are reduced, but device complexity and manufacturing complexity increase
Solution Approach 1:
The memory device is divided into multiple blocks, each with its own separate ground select lines. This segmentation allows independent control of ground select lines for different blocks, enabling reduced Vpass disturb in active blocks while maintaining simpler control for inactive blocks, thus balancing power consumption reduction with device complexity management
Solution Approach 2:
The patent introduces a block dimension to the memory architecture, organizing memory cells into multiple blocks that can be independently controlled. This dimensional organization allows ground select lines to be selectively activated per block, reducing overall power consumption while keeping the control structure manageable through hierarchical organization
2Object-affected harmful factors
If the number of ground select lines is increased to reduce Vpass disturb, then Vpass disturb is reduced, but the number of select lines and manufacturing complexity increase
Solution Approach 1:
Ground select lines are segmented and assigned to specific blocks rather than spanning entire arrays. This segmentation reduces the number of ground select lines needed per block while achieving Vpass disturb reduction, thereby improving ease of manufacture compared to having ground select lines for every possible cell location
Solution Approach 2:
Ground select lines are configured with local quality by assigning them to specific blocks where they are needed. This localized configuration reduces the total number of ground select lines required across the entire device, making manufacturing easier while still achieving Vpass disturb reduction in the relevant blocks
3Quantity of substance
If parallelogram and twisted array arrangements are used to increase bit line density, then bit density increases and power consumption decreases, but device complexity increases
Solution Approach 1:
The patent employs parallelogram and twisted array arrangements that utilize non-traditional geometric configurations in the bit line direction. These arrangements increase bit line density by efficiently packing pillars in oblique or twisted patterns rather than simple rectangular grids, achieving higher bit density while managing device complexity through systematic geometric patterns
Solution Approach 2:
The twisted array arrangement introduces a curved or spiraling pattern to the otherwise linear array of pillars. This curvature allows more pillars to be packed into the available space along the bit line direction, increasing bit density while maintaining a regular, manufacturable pattern that doesn't excessively increase device complexity
Data Source
AI summary
Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into separate word lines, each defining a block of memory cells. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. String select lines run above the conductive layers, each intersection of a pillar and an string select line defining a respective select gate of the pillar. Bit lines run above the SSLs. Ground select lines run below the conductive layers, each intersection of a pillar and a ground select line defining a respective ground select gate of the pillar. The ground select lines are divided laterally such that the number of ground select lines in each block is greater than 1 but less than the number of string select lines in the block.