3D NAND Embedded Hard Mask Layout for Overlay-Controlled Etching
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Solution Overview
Problem
The challenge of fabricating three-dimensional (3D) NAND flash memory devices lies in the high aspect ratio structures, such as channel holes, gate line slits, word line contacts, and bit line contacts, which are difficult to manufacture due to process technology limitations and require precise alignment, leading to reliability issues and defects like bit line to word line shorts.
Innovation Solution
A method for forming 3D memory devices involves creating an alternating dielectric stack with embedded hard masks and sacrificial hard masks, allowing for precise alignment and etching to form vertical structures like dummy channel holes, gate line slits, staircase contacts, and bit line contacts, using different dielectric materials for each mask to ensure accurate dimensions and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of vertically stacked layers is increased to increase storage capacity, then storage density is improved, but manufacturing precision deteriorates due to high aspect ratio structures
Solution Approach 1:
The patent divides the formation of multiple vertical structures into separate etching steps, each with its own dedicated hard mask pattern. Instead of forming all structures (channel holes, gate line slits, word line contacts, bit line contacts) in a single step, the process segments them into sequential steps, allowing each structure to be precisely aligned and formed independently with optimized etching parameters for that specific structure type.
Solution Approach 2:
The patent forms hard mask patterns for all vertical structures beforehand before performing the actual etching. The embedded hard masks are prepared in advance with precise patterns, and sacrificial hard masks are formed to protect certain areas during etching. This preliminary preparation ensures that when etching occurs, the alignment and dimensions are already predetermined, improving manufacturing precision even as the number of stacked layers increases.
2Ease of manufacture
If conventional etching methods are used for high aspect ratio structures, then process simplicity is maintained, but reliability deteriorates due to defects like bit line to word line shorts
Solution Approach 1:
The patent introduces sacrificial hard masks as intermediary protective layers during the etching process. These sacrificial masks are formed on specific areas that should not be etched (such as protecting word line areas during bit line contact formation). They act as mediators that prevent unwanted etching and short circuits, and are subsequently removed after serving their protective function, thereby improving reliability without significantly complicating the overall process.
Solution Approach 2:
The embedded hard masks are formed beforehand with precise patterns that define the exact locations and dimensions of vertical structures. This preliminary patterning ensures that etching only occurs where intended, preventing defects such as bit line to word line shorts. The pre-formed masks serve as templates that guide the etching process, improving reliability by ensuring precise structural formation.
3Productivity
If multiple vertical structures are formed in a single etching step, then productivity is improved, but manufacturing precision deteriorates due to alignment difficulties
Solution Approach 1:
The patent segments the formation of multiple vertical structures into separate etching steps rather than attempting to form them all in a single step. Each etching step focuses on forming one specific type of structure (e.g., channel holes first, then gate line slits, then contacts), allowing for better control and precision in each step while maintaining overall productivity through efficient process sequencing.
Solution Approach 2:
The patent forms embedded hard mask patterns beforehand that serve as precise alignment references for subsequent etching steps. These pre-formed patterns ensure that when multiple vertical structures are formed sequentially, they maintain precise overlay and alignment relationships, solving the alignment difficulties that would otherwise occur when forming multiple structures in separate steps.
Data Source
AI summary
The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes forming an alternating dielectric stack on a substrate, wherein the alternating dielectric stack includes a plurality of dielectric layer pairs, each dielectric layer pair comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer. The method also includes forming a staircase structure in the alternating dielectric stack and disposing an insulating layer on the staircase structure and the alternating dielectric stack. The method further includes forming an embedded hard mask on the insulating layer, wherein the embedded hard mask includes two or more sets of patterns configured to form two or more sets of vertical structures that are fabricated sequentially. The two or more sets of patterns are embedded in the 3D memory device.