3D NAND Peripheral Circuit Stacking for High-Voltage Area Reduction
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Solution Overview
Problem
The challenge lies in reducing the planar area occupied by peripheral circuits in 3D memory devices while maintaining performance and scalability, as scaling down transistor size leads to increased costs and leakage current, and the high voltage requirements of 3D NAND Flash memory devices hinder the reduction of peripheral circuit sizes.
Innovation Solution
The solution involves stacking peripheral circuits in different planes vertically, separating high-voltage and low-voltage circuits, and using hybrid bonding and transfer bonding techniques to reduce chip size and fabrication complexity, allowing for independent thermal budgets and the use of materials like copper for interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If peripheral circuits are scaled down to reduce planar area, then chip size is reduced, but transistor leakage current increases and fabrication costs increase
Solution Approach 1:
The patent transitions from planar 2D arrangement to three-dimensional stacking, placing peripheral circuits in separate semiconductor structures stacked vertically above the memory cell array. This vertical integration reduces the planar footprint while maintaining circuit functionality and allowing independent scaling of transistors without increasing leakage.
Solution Approach 2:
The patent divides the memory device into multiple independent semiconductor structures: a first structure containing the memory cell array and separate second and third structures containing peripheral circuits. This segmentation allows each component to be optimized independently, with peripheral circuits using different transistor sizes and fabrication parameters than the memory cells, thereby reducing leakage while minimizing planar area.
2Ease of manufacture
If peripheral circuits are separated from memory cell arrays, then fabrication can be optimized independently, but device complexity increases
Solution Approach 1:
The patent combines multiple independently fabricated semiconductor structures into a single integrated device through bonding interfaces. The memory cell array structure and peripheral circuit structures are merged vertically, allowing independent optimization of fabrication processes for each component while achieving a unified functional device with reduced overall complexity.
Solution Approach 2:
By stacking semiconductor structures in the vertical dimension rather than arranging them laterally, the patent reduces the complexity of interconnections and packaging. The vertical integration allows simpler bonding processes compared to lateral assembly, and reduces the overall device footprint while maintaining independent fabrication capabilities.
3Reliability
If high voltage requirements are maintained for 3D NAND Flash, then memory performance is preserved, but peripheral circuit size reduction is hindered
Solution Approach 1:
The patent segments the device into memory cell structures requiring high voltage and peripheral circuit structures that can operate at lower voltages. By placing these in separate stacked semiconductor structures, the peripheral circuits can be miniimized in size without compromising the high voltage performance of the memory array, as each structure can be independently optimized for its voltage requirements.
Data Source
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the first semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The second peripheral circuit is between the second bonding interface and the third semiconductor layer.