3D NAND Memory Stack Structure for Multi-Stage Hole Formation
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Solution Overview
Problem
Manufacturing semiconductor memory devices with a three-dimensional structure faces challenges in forming holes through stacked bodies as the number of stacks increases, making it difficult to enhance memory capacity per surface area effectively.
Innovation Solution
The semiconductor memory device design includes a first and second stacked body with an intermediate conductive and insulating layer, a semiconductor pillar with shifted parts, and a charge storage film containing nitrogen, hafnium, or aluminum, where the insulating film between the intermediate conductive layer and the semiconductor pillar reduces threshold voltage fluctuations and allows for efficient hole formation, enabling increased stack numbers and memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacks in the stacked body is increased to enhance memory capacity per surface area, then the memory capacity increases, but it becomes difficult to form holes through the stacked body by collective patterning
Solution Approach 1:
The patent divides the hole formation process into multiple stages: first forming holes through the lower stacked body, then forming holes through the upper stacked body separately. This segmentation allows each hole formation step to be optimized independently, making it feasible to manufacture devices with increased number of stacks that would be impossible to form in a single collective patterning step.
2Quantity of substance
If the number of stacks is increased, then the memory capacity per surface area increases, but the manufacturing precision for hole formation deteriorates
Solution Approach 1:
By segmenting the hole formation into separate steps for lower and upper stacked bodies, each step can be performed with optimized precision control. This avoids the cumulative error that would occur in a single multi-stack hole formation process, thereby maintaining manufacturing precision even as the total number of stacks increases.
Solution Approach 2:
The patent performs preliminary hole formation in the lower stacked body before forming holes in the upper stacked body. This preliminary action establishes a foundation that facilitates subsequent hole formation with higher precision, as the structural context is already prepared and controlled.
3Productivity
If collective patterning is used for hole formation, then the manufacturing efficiency is maintained, but it becomes impossible to form holes when the number of stacks is large
Solution Approach 1:
The patent segments the collective patterning process into multiple sequential collective patterning steps, each handling a subset of stacks. This allows the efficient collective patterning method to be applied repeatedly to different portions of the device, maintaining high manufacturing efficiency while achieving the versatility needed for devices with large numbers of stacks.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.