3D NAND Flash Memory Initialization and Programming Method
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Solution Overview
Problem
The challenge in downscaling NAND flash memory devices lies in the difficulty of reducing the sensing margin and interlayer disturbances in 3D memory cell arrays, particularly in achieving sharp threshold voltage distributions for string selection transistors without disturbing unselected memory cells during programming.
Innovation Solution
A method for initializing and programming 3D non-volatile memory devices involves applying specific voltages to string selection lines and wordlines, using incremental step pulse programming (ISPP) to set target threshold voltages for string selection transistors, and employing program-inhibition techniques to prevent disturbances between selected and unselected memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional programming methods are applied to 3D NAND flash memory devices, then programming operation can be performed, but interlayer disturbances occur between selected and unselected memory cells
Solution Approach 1:
The memory array is segmented into selected and unselected memory cells through the use of string selection transistors with distinct threshold voltage distributions. Program inhibition is applied selectively to unselected memory cells by controlling the string selection transistors, thereby segmenting the programming action spatially and preventing interlayer disturbances.
Solution Approach 2:
Different threshold voltage characteristics are assigned to different groups of string selection transistors based on their location (selected vs. unselected). The first group of string selection transistors has a first threshold voltage distribution while the second group has a second threshold voltage distribution, enabling localized control and program inhibition in unselected regions without affecting selected memory cells.
2Adaptability or versatility
If string selection transistors are programmed to enable memory layer selection, then layer selection capability is achieved, but threshold voltage distribution becomes broad rather than sharp
Solution Approach 1:
The string selection transistors are divided into multiple groups with different threshold voltage distributions. The first group is programmed to a first threshold voltage distribution while the second group is programmed to a second threshold voltage distribution. This segmentation allows sharp threshold voltage characteristics within each group while maintaining the overall capability to select different memory layers through combined control of multiple groups.
Solution Approach 2:
Different threshold voltage parameters are assigned to different groups of string selection transistors. By changing the threshold voltage parameter from a single uniform value to multiple distinct distributions across different groups, the system achieves both sharp threshold voltage characteristics and versatile memory layer selection capability.
3Quantity of substance
If 3D NAND flash memory device is downscaled to increase integration density, then more memory cells can be packed, but sensing margin is reduced
Solution Approach 1:
The patent transitions from 2D to 3D memory architecture by stacking multiple memory layers vertically. This dimensional change allows significantly increased integration density while maintaining adequate sensing margins through the use of string selection transistors with carefully controlled threshold voltage distributions that enable precise selection and isolation of memory cells even in the scaled 3D structure.
Data Source
AI summary
A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selection transistors.