3D NAND Flash Memory Initialization Using Time-Varying Erase Signals
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Solution Overview
Problem
The challenge in downscaling NAND flash memory devices lies in the difficulty of reducing the sensing margin with fewer electrons stored in data storage elements and disturbances between memory cells, particularly in 3D NAND flash memory devices, where conventional 2D memory cell array architectures reach their limits.
Innovation Solution
A method for initializing and programming 3D non-volatile memory devices involves leveling threshold voltages of string selection transistors across multiple memory layers using time-varying erase voltage signals, ensuring precise control over string selection lines to set threshold voltages without disturbances between selected and unselected memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional 2D memory cell array architecture is used, then manufacturing cost is reduced, but downscaling becomes difficult and sensing margin is reduced
Solution Approach 1:
The patent transitions from conventional 2D memory cell array architecture to a 3D memory structure with stacked memory layers. This dimensional change enables continued downscaling and increased storage density by utilizing the vertical dimension, allowing multiple memory layers to be stacked while maintaining manufacturability and sensing margin through the novel initialization approach for string selection transistors in each layer.
2Ease of operation
If string selection transistors are programmed to select memory layers, then layer selection is achieved, but disturbances between memory layers occur
Solution Approach 1:
The patent applies preliminary initialization to string selection transistors before programming operations. By initializing the threshold voltages of string selection transistors in all memory layers to a predetermined level before layer selection, the patent prevents disturbances to unselected memory layers during programming operations, enabling reliable layer selection without harmful side effects.
Solution Approach 2:
The patent utilizes time-varying erase voltage signals with different voltage levels applied at different time periods to initialize string selection transistors. By dynamically changing the voltage parameters during initialization, the patent achieves precise control over threshold voltages, enabling layer selection while preventing disturbances to unselected layers through controlled voltage application sequences.
3Productivity
If programming operation is performed quickly, then timing sequence is reduced, but data integrity and prevention of disturbances must be maintained
Solution Approach 1:
The patent performs initialization of string selection transistors as a preliminary action before programming operations. This pre-initialization ensures that threshold voltages are set to predetermined levels, creating a stable baseline that enables subsequent programming operations to proceed quickly while maintaining data integrity and preventing disturbances, as the initialization is completed in advance.
Solution Approach 2:
The patent implements a continuous initialization process using time-varying voltage signals that maintain useful action throughout the initialization period. By applying voltage signals that evolve over time rather than static voltages, the patent ensures continuous control over the initialization process, enabling both rapid execution and reliable establishment of threshold voltages for data integrity.
Data Source
AI summary
A method of controlling a 3D non-volatile memory device includes initially leveling threshold voltages of the string selection transistors disposed in one or more of the plurality of memory layers to have a predetermined target level; applying a first time varying erase voltage signal having a first time varying section to a first plurality of channel lines of a first memory layer selected among the plurality of memory layers comprising the initially leveled string selection transistors; and setting threshold voltages of the initially leveled string selection transistors in the first memory layer by controlling each of the plurality of string selection lines respectively coupled with the initially leveled string selection transistors during the first time varying section of the first time varying erase voltage signal.