3D NAND Interdeck Source Layout for Lower Channel Resistance
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Solution Overview
Problem
The challenge in forming 3D NAND memory devices is the electrical resistance of channel structures, which limits the vertical height of the channel and consequently restricts the number of word line tiers that can be included in the stack, affecting the design and fabrication of microelectronic devices.
Innovation Solution
The introduction of an interdeck source region, where a source region is vertically interposed between two decks, allowing pillars to extend from this region to both drain regions, effectively halving the channel height and reducing electrical resistance, enabling twice as many word line tiers by allowing N number of tiers in each deck.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the vertical height of the channel is increased to include more word line tiers, then the storage capacity is improved, but the electrical resistance of the channel structure increases
Solution Approach 1:
The channel structure is segmented into multiple decks, each containing a subset of word line tiers. The source region is divided and placed at different vertical levels between decks, creating separate channel paths for each deck. This segmentation allows each channel to maintain a manageable height with lower resistance while the overall device achieves high storage capacity through multiple decks working in parallel.
Solution Approach 2:
The invention transitions from a single vertical channel structure to a multi-deck three-dimensional architecture. By adding the deck dimension and placing source regions at intermediate vertical levels between decks, the design creates multiple shorter channel paths in the vertical direction. This dimensional reorganization reduces channel resistance while maintaining increased storage capacity through the stacked deck configuration.
2Quantity of substance
If the number of word line tiers is increased to enhance storage capacity, then the device complexity increases
Solution Approach 1:
The fabrication process is segmented into modular deck formation steps. Each deck is constructed and integrated independently with standardized processes for forming pillars, insulative structures, and conductive structures. This modular segmentation simplifies the overall fabrication complexity by breaking down the complex multi-tier structure into manageable, repeatable manufacturing units.
Data Source
AI summary
A microelectronic device includes a pair of stack structures. The pair comprises a lower stack structure and an upper stack structure overlying the lower stack structure. The lower stack structure and the upper stack structure each comprise a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A source region is vertically interposed between the lower stack structure and the upper stack structure. A first array of pillars extends through the upper stack structure, from proximate the source region toward a first drain region above the upper stack structure. A second array of pillars extend through the lower stack structure, from proximate the source region toward a second drain region below the lower stack structure. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.