3D NAND Stack Structure With Intermediate Source Layers
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Solution Overview
Problem
Planar processes and fabrication techniques for memory devices have not effectively addressed the storage density of 2D or 3D NAND memory devices, and the storage density of 2D or planar NAND flash memory devices have not effectively addressed the limitations of 2D or planar NAND flash memory, resulting in challenges with feature size and storage density.
Innovation Solution
The implementation of a semiconductor structure with a first stack structure comprising channel structures penetrating through deck and intermediate structures, connected by source layers and an intermediate layer, and further enhanced with bit lines and transistor structures, allowing for improved electrical performance and increased storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar processes are used for memory fabrication, then manufacturing simplicity is maintained, but storage density reaches the upper limit
Solution Approach 1:
The patent transitions from 2D planar NAND architecture to 3D vertically-stacked architecture. Multiple deck structures (first deck structure, second deck structure, third deck structure) are stacked vertically with channel structures penetrating through them, enabling storage density multiplication through the third dimension while maintaining planar manufacturing processes
2Quantity of substance
If feature size is reduced to increase storage density, then storage capacity increases, but fabrication becomes challenging and costly
Solution Approach 1:
Instead of continuing to scale down feature sizes in 2D, the patent stacks multiple identical or similar deck structures vertically. Each deck contains memory cells, and the stack multiplies capacity without requiring further feature size reduction, thus avoiding the fabrication challenges and costs associated with extreme miniaturization
Solution Approach 2:
The memory device is divided into multiple independent deck structures (first, second, third deck structures) that can be manufactured using similar processes and then stacked. This segmentation allows reuse of proven fabrication processes rather than developing new processes for smaller features
3Quantity of substance
If vertically-stacked structures are implemented, then storage density increases, but signal loss and interference between source layers increase
Solution Approach 1:
An intermediate structure is inserted between the first and second deck structures. This intermediate structure contains an intermediate source layer that acts as a mediator, providing electrical connection and signal regeneration between the vertically stacked memory cells, thereby reducing signal loss and interference that would otherwise accumulate through the vertical stack
Solution Approach 2:
The vertical stack is segmented into multiple decks with intermediate structures between them. This segmentation breaks the continuous vertical path into discrete segments, allowing intermediate source layers to refresh and regenerate signals at each segment boundary, preventing cumulative signal degradation
Data Source
AI summary
The present disclosure provides a semiconductor structure and manufacturing method thereof, a memory system, and an electronic device, which relate to the technical field of semiconductor chip. The semiconductor structure includes a first stack structure including a plurality of channel structures, and a first deck structure, a first intermediate structure and the second deck structure that are stacked. The first intermediate structure is stacked between the first deck structure and the second deck structure, and the channel structures penetrate through the first deck structure, the first intermediate structure and the second deck structure along the stack direction. The first intermediate structure includes the first source layer, the second source layer and the intermediate layer disposed between the first source layer and the second source layer, and the first source layer and the second source layer are connected with the channel structure respectively.