3D NAND Memory Interposer for Testing and Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional memory arrays face limitations in increasing memory density and reducing costs due to the technological constraints of reducing memory cell size in two-dimensional structures, prompting the development of three-dimensional NAND architecture semiconductor memory devices.
Innovation Solution
The implementation of a three-dimensional NAND architecture with vertically stacked memory cell strings and advanced management systems, including memory controllers and error correction mechanisms, to enhance memory density and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory array structures are used, then manufacturing and operation are simpler, but memory density cannot be increased beyond technological limits
Solution Approach 1:
The patent transitions from traditional two-dimensional memory array layouts to a three-dimensional stacked architecture where multiple memory die are vertically stacked and interconnected via through-silicon vias (TSVs). This dimensional change enables significantly higher memory density by utilizing the vertical space above each memory die, effectively multiplying the storage capacity without increasing the footprint area.
2Quantity of substance
If memory cell size is reduced in two-dimensional structures, then memory density increases, but manufacturing precision requirements become unmanageable
Solution Approach 1:
Instead of continuing to shrink memory cell dimensions in the planar direction which demands extreme manufacturing precision, the patent stacks multiple complete memory die vertically. Each die maintains standard cell sizes that are within current manufacturing capabilities, while the overall density increases through the vertical stacking of multiple such die.
3Quantity of substance
If three-dimensional NAND architecture is implemented, then memory density increases significantly, but interconnect complexity and signal management become more difficult
Solution Approach 1:
The patent introduces intermediary components including TSVs that penetrate through the substrate to connect stacked die, buffer circuits that manage signal transitions between layers, and control logic that coordinates access across multiple die. These intermediaries simplify the overall system by breaking down the complex interconnect problem into manageable segments.
Solution Approach 2:
The memory system is divided into multiple independent but interconnected memory die, each functioning as a separate unit. This segmentation allows each die to be manufactured and tested independently, then stacked and interconnected through standardized TSV interfaces, reducing the overall interconnect complexity compared to a monolithic three-dimensional structure.
4Quantity of substance
If vertically stacked memory die are used, then memory density increases, but heat dissipation and signal integrity challenges arise
Solution Approach 1:
The patent incorporates thermal management features at specific locations within the stacked structure, such as thermal vias and heat dissipation pathways integrated into the substrate and interconnect layers. These localized thermal management features address heat accumulation problems without requiring a complete redesign of the entire stacked architecture.
Data Source
AI summary
A variety of applications can include a system having a system platform to which a memory system can be attached for operation of the system. With the memory system removed from the system platform or before being attached to the system platform, an interposer can be connected at the location for the memory system on the system platform to facilitate testing of the system with respect to the memory system. The interposer can include a set of electrical connectors embedded on a first side of the interposer to connect to the system platform and a connector embedded on a second side of the interposer opposite the first side, where the connector allows coupling to an external platform to convey signals between the system platform and the external platform. Additional apparatus, systems, and methods are disclosed.