3D NAND Memory Leakage Reduction via Block Biasing
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Solution Overview
Problem
Current 3D NAND memory arrays face challenges in reducing current leakage, particularly in program-inhibited pillars, which increases operation current and power consumption due to the need for biasing the common source to a positive voltage to prevent leakage, affecting both selected and deselected memory blocks.
Innovation Solution
The implementation of different bias voltages for selected and deselected memory blocks, where a first bias voltage is applied to the deselected block and a second bias voltage to the selected block, specifically targeting the select gate drain and source lines to minimize leakage current, thereby reducing the overall operation current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the common source is biased to a positive voltage to prevent leakage current in program-inhibited pillars, then leakage current is reduced, but operation current increases
Solution Approach 1:
The patent applies different bias voltages to different blocks: deselected blocks receive a first bias voltage (e.g., 0V or negative) to minimize leakage current, while selected blocks receive a second bias voltage (e.g., positive voltage) to enable normal operation. This local differentiation resolves the contradiction by reducing leakage current in non-selected blocks without affecting operation current in selected blocks that require programming or reading.
2Object-generated harmful factors
If uniform bias voltage is applied to all blocks, then circuit simplicity is maintained, but leakage current cannot be minimized in deselected blocks
Solution Approach 1:
The patent segments the memory array into selected and deselected blocks, applying different bias voltage configurations to each segment. Deselected blocks are provided with a first bias voltage through dedicated bias circuitry, while selected blocks receive a second bias voltage. This segmentation enables leakage current minimization in deselected blocks without compromising the operational functionality of selected blocks.
3Productivity
If high voltage is applied to selected memory location for programming, then programming efficiency is improved, but inadvertent programming of non-selected cells increases
Solution Approach 1:
The patent applies a first bias voltage (e.g., 0V or negative voltage) to deselected blocks before and during the programming operation on selected blocks. This preliminary anti-action creates a potential barrier that prevents electrons from tunneling into the floating gates of non-selected cells, thereby preventing inadvertent programming while allowing efficient programming of selected cells with high voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage current in 3D NAND memory arrays by optimizing bias voltage configurations, leading to lower power consumption and improved operational efficiency during memory operations.
Implementation Method 1
The high electrical field may cause electrons in the memory cell channel to cross the gate oxide and embed in the floating gate
Implementation Method 2
The high electrical field may cause electrons in the memory cell channel to cross the gate oxide and embed in the floating gate (known as Fowler-Nordheim (F-N) tunneling)
Data Source
AI summary
Embodiments of the present disclosure are directed towards techniques and configurations for providing an apparatus comprising a memory array, to which bias voltage may be provided to reduce leakage current. In one embodiment, the apparatus may comprise a three-dimensional (3D) memory array having at least first and second blocks; and circuitry coupled with the 3D memory array to access the 3D memory array. The circuitry may include circuit to deselect the first block and select the second block, and supply a first bias voltage to the deselected first block and a second bias voltage to the selected second block, to reduce leakage current in the 3D memory array. The first bias voltage may be different than the second bias voltage. Other embodiments may be described and/or claimed.