3D NAND Dual-Deck Channel Interface for Leakage Isolation
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Solution Overview
Problem
In 3D NAND memory devices, the challenge lies in achieving a good overlap between upper and lower channel structures to prevent electrical leakage and shorts, particularly when there is a poor alignment, which can result in voids and word line leakage due to the upper channel extending into adjacent word line layers.
Innovation Solution
A dual deck structure is implemented with a thicker insulating layer in the lower array region at the interface between the upper and lower channel structures, allowing the upper channel to extend into this layer instead of the adjacent word line, thereby preventing electrical leakage and shorts. This structure includes a stack of alternating word line and insulating layers with a specific thickness configuration, where the uppermost insulating layer is significantly thicker than others, and the insulating layers in the staircase region maintain uniform thickness to facilitate etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard thickness insulating layer is used between word line layers, then the device structure remains simple and manufacturing is easier, but the upper channel structure may extend into adjacent lower word line layers causing electrical leakage and shorts
Solution Approach 1:
The patent applies local quality by varying the thickness of insulating layers at specific locations. The particular first insulating layer at the interface between upper and lower channel structures has a greater thickness than other insulating layers in the stack. This localized thickness increase prevents upper channel structures from extending into lower word line layers, thereby preventing electrical leakage and shorts without increasing the complexity of the entire device structure.
2Manufacturing precision
If the upper channel structure is allowed to extend freely, then the manufacturing process is simpler, but voids form in the word line layers and critical dimensions increase leading to performance degradation
Solution Approach 1:
The patent applies beforehand cushioning by forming a thicker particular first insulating layer in advance at the interface region between upper and lower channel structures. This thicker insulating layer acts as a cushion or buffer that maintains proper spacing and alignment between channel structures and word line layers, preventing void formation and critical dimension increases before manufacturing issues can occur.
3Reliability
If multiple insulating layers with varying thicknesses are used to prevent electrical leakage, then reliability improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent implements local quality by making only one particular insulating layer thicker than the others, specifically the first insulating layer at the critical interface region. This selective thickness variation provides the necessary electrical isolation and reliability improvement without requiring all insulating layers to be complex multi-layer structures, thereby limiting the increase in overall device complexity.
Data Source
AI summary
A semiconductor device includes a first stack of alternating first word line layers and first insulating layers over a semiconductor layer. A first channel structure extends from the semiconductor layer and through a first array region of the first stack. A second stack of alternating second word line layers and second insulating layers are over the first stack. A second channel structure extends from the first channel structure and through a second array region of the second stack. A thickness of a particular first insulating layer, which is positioned closest to the second stack relative to other first insulating layers, is a sum of at least two times an average thickness of the other first insulating layers and at least one time an average thickness of the first word line layers in the first array region.