3D NAND Block Architecture for In-Memory MAC With Lower Current
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Solution Overview
Problem
Existing neuromorphic computing systems face challenges in efficiently performing large-scale sum-of-products operations due to high current consumption, dense memory requirements, and high bandwidth data communications, necessitating energy-efficient and flexible solutions.
Innovation Solution
Implementing a method and circuit using a plurality of NAND blocks based on 3D NAND flash technology for in-memory computation, where coefficient data is stored in memory cells and inputs are applied to bit lines and string select lines, combining currents to generate an output signal representing the sum-of-products.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a very large array is used to execute many operations in parallel, then productivity is improved, but current consumption increases
Solution Approach 1:
The system divides the large array into multiple blocks, each block independently performing sum-of-products operations. This segmentation allows parallel execution across blocks while limiting the current consumption of each individual block, thus achieving high productivity without proportionally increasing total current consumption.
Solution Approach 2:
The patent transitions from traditional planar memory arrays to three-dimensional stacked memory architecture. By utilizing the vertical dimension with multiple layers and bit lines stacked in three dimensions, the system achieves higher computational density and parallelism without proportionally increasing current consumption, as the vertical stacking allows more operations to share the same current budget.
2Manufacturing precision
If dense memory is used for large scale matrix multiplication, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent merges memory storage and computation functions into a single integrated structure. Memory cells store coefficients while simultaneously performing multiply-and-accumulate operations when activated. This combination eliminates the need for separate high-bandwidth communication channels between memory and processing units, reducing device complexity while maintaining high memory density.
Solution Approach 2:
The memory cells are designed to serve multiple functions: storing data, performing computation, and generating output signals. The same memory array structure is used for both coefficient storage and MAC operations, eliminating the need for dedicated communication infrastructure and reducing overall system complexity.
3Loss of energy
If in-memory computation is implemented, then energy efficiency is improved, but adaptability decreases
Solution Approach 1:
The system employs dynamically controllable string select lines that can selectively activate different columns of memory cells. This dynamic control allows the same physical memory structure to adapt to different computational requirements by enabling or disabling specific cell groups, maintaining computational flexibility while preserving the energy efficiency of in-memory computation.
Solution Approach 2:
The patent uses variable voltage levels applied to string select lines to control the activation state of memory cells. By changing the voltage parameter on select lines, the system can dynamically reconfigure which memory cells participate in computation, providing adaptability without requiring data movement between memory and processing units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high throughput and energy-efficient multiply-and-accumulate operations, capable of executing tera-operations per watt, suitable for machine learning systems and neural networks.
Implementation Method 1
storing coefficient data w(i,j) for a product term X(i)*W(i) in cells on a level L(k) of a NAND block
Implementation Method 2
simultaneously applying inputs X(i) to bit lines BL(1) to BL(B), and string select voltages to string select lines SSL(1) to SSL(S), and a word line compute voltage to cells in the selected word line level
Implementation Method 3
combining currents through the columns C(1) to C(B) of NAND strings connected to bit lines BL(1) to BL(B) on a plurality of source lines for the NAND block
Data Source
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AI summary
A circuit for in-memory multiply-and-accumulate functions includes a plurality of NAND blocks. A NAND block includes an array of NAND strings, including B columns and S rows, and L levels of memory cells. W word lines are coupled to (B*S) memory cells in respective levels in the L levels. A source line is coupled to the (B*S) NAND strings in the block. String select line drivers supply voltages to connect NAND strings on multiple string select lines to corresponding bit lines simultaneously. Word line drivers are coupled to apply word line voltages to a word line or word lines in a selected level. A plurality of bit line drivers apply input data to the B bit lines simultaneously. A current sensing circuit is coupled to the source line.