3D NAND Memory Array Stacks With Replacement-Gate Conductive Tiers
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Solution Overview
Problem
Existing memory array architectures face challenges in efficiently forming vertically-stacked memory cells with reliable electrical connections and structural integrity, particularly in NAND architectures, which affect data retention and access performance.
Innovation Solution
A method involving the formation of a stack with alternating conductive and insulative tiers, where sacrificial materials are replaced with conducting materials to create vertically-stacked memory cells, ensuring reliable electrical connections and structural integrity through the use of 'gate-last' or 'replacement-gate' processing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertically-stacked memory cells are formed using conventional processing techniques, then memory array structure is achieved, but electrical connections and structural integrity are unreliable
Solution Approach 1:
The patent applies preliminary action by forming sacrificial material tiers (first and second sacrificial materials) in specific positions before forming the final conductive structures. These sacrificial materials are strategically placed to define future wordline and bitline positions, and are removed later to create precise conductive pathways. This preliminary structuring enables reliable electrical connections while simplifying the overall fabrication process.
Solution Approach 2:
The patent uses sacrificial materials as intermediary elements during fabrication. These temporary structures (first sacrificial material for wordlines, second sacrificial material for bitlines) act as mediators that guide the formation of conductive tiers. The sacrificial materials are removed after serving their structural guidance purpose, leaving clean conductive pathways without direct contact between adjacent wordlines and bitlines, thus ensuring structural integrity.
2Reliability
If memory arrays are arranged in vertically-stacked configurations, then data retention and access performance are improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the memory array into distinct vertically-stacked functional units. Each memory cell is divided into separate conductive tiers (first conductive tier for wordlines, second conductive tier for bitlines) that are spatially separated by insulative materials. This segmentation allows independent control and formation of each conductive layer, simplifying the manufacturing process while achieving reliable vertically-stacked memory structures with improved data retention and access performance.
Solution Approach 2:
The patent transitions from planar to three-dimensional vertically-stacked architecture by adding the vertical dimension to memory cell organization. Conductive tiers are stacked elevationally with insulative tiers in between, creating a multi-layer structure that increases storage density and improves access performance. The gate-last processing technique enables this dimensional transition by forming gates after the vertical stack is established, simplifying the complex 3D fabrication process.
3Reliability
If gate-last or replacement-gate processing techniques are used, then structural integrity is improved, but manufacturing steps increase
Solution Approach 1:
The patent merges multiple fabrication operations into integrated processing steps. The gate-last technique combines the formation of conductive tiers, insulative tiers, and gate structures into a unified vertical stacking process. Sacrificial material removal, conductive material deposition, and gate formation are combined in a sequence that maintains structural integrity throughout. This merging of operations improves structural integrity while managing fabrication complexity through systematic integration of steps.
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating conductive tiers and insulative tiers. The stack comprises laterally-spaced memory-block regions. The lower portion comprises multiple lower of the conductive tiers and multiple lower of the insulative tiers. The lower insulative tiers comprise insulative material. The lower conductive tiers comprise sacrificial material that is of different composition from that of the insulative material. The sacrificial material is replaced with conducting material. After the replacing of the sacrificial material, the vertically-alternating conductive tiers and insulative tiers of an upper portion of the stack are formed above the lower portion. The upper portion comprises multiple upper of the conductive tiers and multiple upper of the insulative tiers. The upper insulative tiers comprise insulating material. The upper conductive tiers comprise sacrifice material that is of different composition from that of the conducting material, the insulating material, and the insulative material. The sacrifice material is replaced with conductive material. Other embodiments, including structure independent of method, are disclosed.