3D NAND Memory Control for Low-Disturbance Sub-Block Erasing
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Solution Overview
Problem
Existing NAND type flash memories face challenges in improving operational reliability, particularly in three-dimensional laminated structures, due to issues such as program disturbance and inefficient erasing methods.
Innovation Solution
The semiconductor storage device employs a control circuit that performs specific voltage and select voltage operations on word and select gate lines to manage data writing and erasing, utilizing two distinct write modes (WL increment and string increment) and two erasing methods (block and sub-block) to enhance reliability and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional laminated NAND type flash memory is used to increase storage capacity, then storage density is improved, but program disturbance occurs and operational reliability deteriorates
Solution Approach 1:
The memory device is divided into multiple blocks, and each block is further divided into multiple sub-blocks. This segmentation allows selective erasing of only the sub-block containing invalid data, rather than erasing the entire block. By isolating and treating only the affected sub-block, program disturbance in other areas is prevented, thereby maintaining operational reliability while preserving storage capacity.
Solution Approach 2:
The patent implements local quality by applying different operations to different regions of the memory device. Specifically, only the sub-block containing invalid data undergoes erasing, while other sub-blocks remain unaffected. This localized approach ensures that program disturbance is contained to minimal areas, preserving the reliability of the overall storage system while maintaining high storage density.
2Ease of operation
If traditional block erasing method is used, then erasing operation is simple, but erasing efficiency deteriorates when only partial data needs to be erased
Solution Approach 1:
The block is segmented into multiple sub-blocks, enabling selective erasing operations. Instead of erasing the entire block, the controller can identify and erase only the specific sub-block containing invalid data. This maintains operational simplicity through automated controller management while dramatically improving erasing efficiency by avoiding unnecessary erasure of valid data in other sub-blocks.
Solution Approach 2:
The controller performs preliminary identification of invalid data locations before initiating erasing operations. By pre-locating the sub-block containing invalid data through metadata tracking or scanning, the system prepares for targeted erasing, thus improving efficiency without complicating the user interface or operation flow.
3Productivity
If selective sub-block erasing is implemented, then erasing efficiency is improved, but device complexity increases
Solution Approach 1:
The controller acts as an intermediary that manages the complexity of sub-block segmentation and selective erasing. The controller tracks the status of each sub-block and automatically determines which sub-blocks require erasing, shielding the user from complexity while enabling efficient selective erasure operations. This intermediary layer handles the sophisticated logic needed for high-efficiency erasing without exposing complexity to the user.
Data Source
AI summary
A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.