3D NAND Memory Device Vertical Stacking and Epitaxial Contact
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Solution Overview
Problem
Three-dimensional NAND-type flash memory devices face challenges in maintaining sufficient ON/OFF characteristics and cell current flow due to limitations in lithography technology, which affect the integration and performance of selection transistors in laminated structures.
Innovation Solution
A nonvolatile semiconductor memory device with a laminated structure featuring a columnar semiconductor layer and a charge storage layer, where the semiconductor layers are formed in a staircase pattern to enhance the array density and include an epitaxial layer for improved electrical contact, and the use of specific materials like silicon nitride for the charge storage layer to optimize threshold voltage and cell characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If lithography technology is used to fabricate three-dimensional NAND-type flash memory, then device integration is achieved, but resolution limits prevent sufficient ON/OFF characteristics and cell current flow
Solution Approach 1:
The patent transitions from planar two-dimensional transistor structures to three-dimensional vertically-stacked transistor structures. Multiple selection transistors are stacked in the vertical dimension, allowing higher integration density while maintaining adequate current flow characteristics through the third dimension, thereby overcoming lithography resolution limits.
Solution Approach 2:
The patent implements nested structures where control gates are wrapped around floating gates in a cylindrical configuration. This nested arrangement allows multiple functional elements to be contained within each other, achieving high integration while maintaining proper electrical characteristics for selection transistors.
2Quantity of substance
If selection transistor density is increased to improve integration, then device capacity increases, but cell current flow deteriorates
Solution Approach 1:
By stacking selection transistors vertically in the third dimension, the patent increases transistor density without compromising horizontal current flow paths. Each stacked transistor maintains its own current channel, ensuring sufficient cell current flow even as density increases through vertical stacking.
Solution Approach 2:
The patent applies different material compositions and structural configurations to different regions of the selection transistors. Control gates and floating gates use specific materials optimized for their local functions, ensuring that each region contributes optimally to overall current flow while maintaining high density.
Data Source
AI summary
One embodiment includes: forming a laminated body by alternately laminating a conducting layer and an interlayer insulating layer on a substrate; forming a memory hole passing through the laminated body; forming a memory gate insulating layer including a charge storage layer on an inner wall of the memory hole; forming a first semiconductor layer on the memory gate insulating layer; forming a cover film on the first semiconductor layer; removing the memory gate insulating layer, the first semiconductor layer, and the cover film on a bottom surface of the memory hole, to expose the substrate; forming an epitaxial layer on the exposed substrate; removing the cover film; and forming the second semiconductor layer along the first semiconductor layer, to electrically couple: the substrate to the first semiconductor layer; and the substrate to the second semiconductor layer, via the epitaxial layer.