3D NAND Memory Finger Architecture for Density and Fabrication Complexity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to limitations in feature size and fabrication costs, leading to density constraints, which 3D memory architecture aims to address by increasing memory density through vertical memory strings and bitlines.
Innovation Solution
A 3D memory device structure featuring alternating conductor/dielectric layer pairs with vertical memory strings and bitlines, where the channel hole pitch is significantly larger than the bitline pitch, allowing for efficient memory finger formation and reduced fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell feature sizes are reduced to increase density, then memory density is improved, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar 2D memory cell architecture to 3D vertical memory strings, where memory cells are stacked vertically rather than arranged in a plane. This dimensional change allows continued density improvement without further reducing lateral feature sizes, thereby avoiding the fabrication complexity and cost increases associated with extreme planar scaling.
Solution Approach 2:
The memory array is divided into multiple memory fingers, each with its own set of bitlines and wordlines. This segmentation allows independent optimization and fabrication of each finger, reducing overall fabrication complexity while achieving high total density through parallel structures.
2Quantity of substance
If memory finger size is increased to improve density, then memory density is improved, but read and programming times increase due to longer wordlines and larger time constants
Solution Approach 1:
By stacking memory cells vertically in 3D, the patent achieves increased memory finger density without proportionally increasing wordline length. The vertical stacking allows more cells to be accessed through the same wordline infrastructure, improving density while maintaining shorter wordline lengths and smaller time constants for faster read and programming operations.
Solution Approach 2:
The patent optimizes the local geometry of vertical memory strings and channel holes to improve electrical characteristics. By controlling the dimensions and spacing of vertical structures, the patent achieves high density while maintaining favorable resistance and capacitance values that enable faster operation.
3Quantity of substance
If channel hole pitch is reduced to increase density, then memory density is improved, but bitline pitch and fabrication precision requirements increase
Solution Approach 1:
The patent achieves higher density by reducing channel hole pitch in the vertical dimension through stacked memory cells, while maintaining larger lateral bitline pitch. This separates the density improvement mechanism (vertical stacking with reduced channel hole pitch) from the interconnect spacing (lateral bitline pitch), allowing high density without excessive precision requirements for bitline fabrication.
Data Source
AI summary
Embodiments of a memory finger structure and architecture for a three-dimensional memory device and fabrication method thereof are disclosed. The method includes forming an alternating layer stack, forming a plurality of slit structures, forming a plurality of conductor/dielectric layer pairs, forming a first column of vertical memory strings, forming a second column of vertical memory strings, and forming a plurality of bitlines. The plurality of slit structures each extend vertically through the alternating layer stack and laterally along a wordline direction to divide the alternating layer stack into at least one memory finger. The vertical memory strings in the first column are displaced relative to each other along the wordline direction. The vertical memory strings in the second column are displaced relative to each other along the wordline direction. Each bitline is connected to an individual vertical memory string in the first and second columns.