3D NAND Memory Pillar Layout for Higher Density Storage
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Solution Overview
Problem
Existing NAND flash memory devices face challenges in achieving high integration and large capacity while maintaining efficient data storage and retrieval operations.
Innovation Solution
A memory device with a three-dimensional memory structure, including a substrate, semiconductor layers, wiring layers, memory pillars, and contacts, is designed to enhance data storage capacity and integration by optimizing the arrangement and connectivity of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is adopted for high integration, then storage capacity increases, but device complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory structures to three-dimensional stacked structures, where memory cells are arranged vertically across multiple layers. This dimensional change enables significantly higher storage capacity within the same footprint by utilizing the vertical dimension for stacking multiple memory cell layers, thereby resolving the contradiction between storage capacity and device complexity.
Solution Approach 2:
The patent implements a nested structure where multiple memory cell layers are stacked vertically, with each layer containing memory cells formed over corresponding wiring layers. The contacts extend through multiple insulating layers to reach semiconductor regions in underlying layers, creating a nested configuration that maximizes storage density while managing structural complexity through systematic layering.
2Quantity of substance
If multiple wiring layers and memory pillars are arranged in three dimensions, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory device into distinct segmented layers including multiple insulating layers, wiring layers, and memory cell layers. Each layer is formed separately with defined functions, allowing for modular manufacturing processes. The contacts are segmented to extend through specific insulating layers while being insulated from certain wiring layers, enabling precise control over electrical connections and reducing manufacturing precision requirements.
Solution Approach 2:
The patent applies local quality by providing different insulating characteristics at different locations and layers. Specific insulating layers are positioned between contacts and wiring layers to provide electrical insulation only where needed, while allowing electrical connection at other locations. This localized approach to insulation enables complex three-dimensional wiring and memory pillar arrangements with manageable manufacturing precision requirements.
Data Source
AI summary
A semiconductor device includes a substrate, first and second semiconductor layers arranged in this order apart from each other in a first direction; first wiring layers arranged apart from each other in the first direction between the substrate and the first semiconductor layer and including a first layer; second wiring layers arranged apart from each other in the first direction between the first and second semiconductor layers and including a second layer; first and second memory pillars extending in the first direction and having portions that intersect the respective first and second wiring layers and function as memory cells; and a first contact extending in the first direction to intersect with the first wiring layers, being in contact with the first layer, being insulated from the first wiring layers excluding the first layer and the first semiconductor layer, and electrically connecting the substrate and the second layer.