3D NAND Memory Device Plane Boundary Pattern Disruption
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in increasing bandwidth and capacity while maintaining a high chip occupancy ratio for memory cell arrays, as the number of planes increases, leading to reduced efficiency and potential pattern disruptions at boundaries between planes.
Innovation Solution
The semiconductor memory device employs a three-dimensional NAND flash memory architecture with a control chip and memory chip bonded via wafer bonding, where the memory cell array is not divided at plane boundaries, maintaining periodicity and eliminating the need for dummy cells, and utilizing an element isolation insulating layer that penetrates the substrate to reduce chip occupancy and enhance capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of planes is increased to increase bandwidth and capacity, then the storage capacity and bandwidth are improved, but the chip occupancy ratio for memory cell arrays is reduced and pattern disruptions occur at plane boundaries
Solution Approach 1:
The patent transitions from a two-dimensional plane-based architecture to a three-dimensional stacked architecture. Multiple memory cell arrays are stacked vertically along the third dimension, allowing increased storage capacity without proportionally increasing the footprint area on each chip. This dimensional change enables higher capacity while maintaining efficient chip occupancy.
Solution Approach 2:
The memory device is divided into multiple independent memory cell arrays that are stacked vertically. Each memory cell array can be independently formed and then bonded to others, allowing flexible configuration without pattern disruptions at boundaries. The segmentation into separate stacks eliminates the boundary issues that occur in planar multi-plane architectures.
2Adaptability or versatility
If wafer bonding is used to bond control chip and memory chip, then integration functionality is improved, but manufacturing process complexity increases
Solution Approach 1:
The control circuit and memory cell array are formed on separate wafers before bonding. All necessary circuit patterns, interconnect structures, and memory cell formations are completed in advance on各自的 wafers. This preliminary preparation simplifies the bonding process itself, as it only requires aligning and bonding the pre-formed structures rather than forming complex integrated structures during bonding.
Solution Approach 2:
The patent uses metal pads as intermediary bonding elements between the control chip and memory chip. The metal pads on both wafers serve as bonding interfaces that facilitate the wafer bonding process. These intermediary bonding structures simplify the manufacturing by providing standardized interfaces for bonding, reducing the complexity of direct chip-to-chip integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a significant increase in the number of planes, thereby achieving a large bandwidth and high-capacity flash memory with reduced chip occupancy ratio and minimized pattern disruptions, enabling efficient data storage without compromising memory cell functionality.
Implementation Method 1
Wafer bonding technology provides highly functional or highly integrated semiconductor devices by bonding two wafers, each having an integrated circuit formed thereon
Data Source
AI summary
A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.