3D NAND Memory Programming with Reduced Disturbance
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, 3D memory architecture is needed to overcome density limitations and reduce the challenges and costs associated with planar memory cell fabrication, while minimizing disturbances in programming operations of 3D NAND memory devices.
Innovation Solution
A novel programming scheme for 3D NAND memory devices that applies reduced channel pass voltage and uses dummy memory layers to prevent leakage and channel hot electron injection, with specific voltage gradients and cut-off voltages to minimize disturbances during programming operations across multiple memory decks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D memory architecture is used to overcome density limitations, then memory density is improved, but programming disturbances and leakage currents increase
Solution Approach 1:
The memory stack is divided into multiple decks (first deck, second deck, third deck) with intermediate dummy memory layers between them. This segmentation isolates programming operations in one deck from affecting other decks, reducing cross-deck disturbances and leakage currents while maintaining high memory density.
Solution Approach 2:
Intermediate dummy memory layers are introduced between adjacent memory decks to act as intermediaries. These dummy layers block the propagation of hot electrons and leakage currents during programming operations, preventing disturbances from spreading to non-programmed decks while allowing the 3D architecture to maintain high density.
2Speed
If channel pass voltage is applied during programming, then programming speed is improved, but disturbance to non-programmed memory layers increases
Solution Approach 1:
Different voltage levels are applied to different memory decks simultaneously during programming. The first memory deck receives full channel pass voltage for high-speed programming, while the second and third decks receive reduced or zero channel pass voltage to minimize disturbances. This local differentiation allows fast programming where needed while protecting non-programmed areas.
Solution Approach 2:
The channel pass voltage applied to memory decks is made dynamic rather than static. During programming operations, the voltage levels are adjusted in real-time based on which deck is being programmed, allowing the system to optimize between programming speed and disturbance minimization for each deck independently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The scheme effectively reduces channel pass voltage and program voltage disturbances, enhancing the reliability and efficiency of programming operations in multi-deck 3D NAND memory devices by minimizing coupling effects and leakage currents.
Implementation Method 1
uses dummy memory layers to prevent leakage and channel hot electron injection
Implementation Method 2
uses dummy memory layers to prevent leakage and channel hot electron injection
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes memory decks each including memory layers in a vertical direction. Each memory layer in a first memory deck is first programmed. The first programming includes applying a program voltage to the memory layer and a first channel pass voltage smaller than the program voltage to each rest of the memory layers. Each memory layer in a second memory deck above the first memory deck is second programmed. The second programming includes applying the program voltage to the memory layer and the first channel pass voltage to each rest of the memory layers. The second programming further includes applying a second channel pass voltage smaller than the first channel pass voltage to each memory layer in the first memory deck.