3D-NAND In-Memory Search Architecture for Dense Low-Power Matching
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Solution Overview
Problem
Conventional TCAM technologies for big data and AI processing suffer from low memory density and high power usage, while non-volatile implementations require paired memory cells, limiting efficiency in searching and data storage.
Innovation Solution
A 3D-NAND memory array system with integrated data and search encoders, coupled with logic operations modules, enables high-performance searching and sorting by encoding search words and data within the array, using selective logical operations and threshold voltage settings to represent multiple states in each memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional TCAM technology using SRAM techniques is used, then searching functionality is achieved, but memory density is low and power usage is high
Solution Approach 1:
The patent replaces the mechanical/SRAM-based TCAM structure with a non-volatile memory implementation using 2T2R (two transistor two resistor) or 2FeFET (two ferroelectric field-effect transistor) techniques. This substitution eliminates the need for paired memory cells while achieving higher memory density and lower power consumption through non-volatile storage mechanisms that persist data without continuous power supply.
2Use of energy by moving object
If non-volatile memory techniques (2T2R or 2FeFET) are used for TCAM, then power consumption is reduced, but paired memory is required which limits efficiency
Solution Approach 1:
The patent extracts and eliminates the paired memory cell requirement from the TCAM implementation. By using non-volatile memory techniques where a single memory cell can store one bit of data independently, the design removes the need for paired cells, thereby improving storage efficiency and searching productivity while maintaining low power consumption characteristics.
3Quantity of substance
If 3D-NAND memory array is used for in-memory searching, then content density is improved, but complexity of encoding and logic operations increases
Solution Approach 1:
The patent segments the 3D-NAND memory array into multiple portions that can be independently accessed and searched. Each portion can be selectively enabled based on the search operation requirements, allowing parallel processing of multiple search operations simultaneously. This segmentation reduces the effective complexity by dividing the large memory space into manageable units while maintaining high content density.
Solution Approach 2:
The patent implements dynamic enabling of memory portions based on search word characteristics and data storage patterns. The logic operations module dynamically selects which memory portions to access and which logical operations to perform, adapting the search operation to the specific data and search word being processed. This dynamic approach simplifies the overall system by allowing flexible configuration rather than requiring complex fixed-architecture designs.
Data Source
AI summary
A high-level architecture for 3D-NAND based in-memory search provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. A search word is presented to a 3D-NAND memory along a direction of a bit line of the 3D-NAND memory. Each character of the word comprises a number of digits. Each digit is matched against respective layers of the 3D-NAND memory. Each digit is usable to represent one of a plurality of levels according to a selected encoding. Optionally, various lengths of words are accommodated via serial and/or parallel operations of one or more 3D-NAND memories.