3D NAND Memory Segmentation for Partial Erase Control
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Solution Overview
Problem
High-density 3D NAND memories face inefficiencies in erase operations due to large block sizes, making it inconvenient to modify small units of data, especially as the number of layers increases.
Innovation Solution
The memory structure comprises memory segments with a selecting device that allows for partial erasure, featuring a semiconductor gate electrode, channel, gate dielectric layer, and gate electrode layer, enabling selective erasure of memory cells by controlling the selecting device's state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of 3D NAND memories increases, then storage capacity is improved, but block size increases making erase operations less convenient
Solution Approach 1:
The memory structure is divided into multiple memory segments (first memory segment, second memory segment, etc.) within a single block, each with its own selecting device. This segmentation allows independent erasure of individual segments rather than requiring erasure of the entire block, thus maintaining high storage capacity while improving erase operation convenience.
Solution Approach 2:
Each memory segment is equipped with its own selecting device (first selecting device, second selecting device, etc.) that provides localized control. This enables different erasure states to be applied to different segments within the same block, allowing users to erase only the specific segments that need updating while preserving data in other segments.
2Quantity of substance
If the number of layers in stacks increases, then storage capacity is improved, but block size increases leading to larger erase operations
Solution Approach 1:
The multi-layer memory structure is segmented into multiple independent memory segments, each controllable by its own selecting device. This allows erasure operations to be performed on individual segments rather than the entire multi-layer block, significantly reducing the time required for erase operations while maintaining the high storage capacity provided by the increased number of layers.
Solution Approach 2:
Instead of performing full block erasure, the system enables partial erasure of only the specific memory segment that needs to be updated. This partial action approach reduces the erase operation time from what would be required to erase the entire multi-layer block to only the necessary portion.
Data Source
AI summary
A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises memory segments. Each of the memory segments comprises a memory array region, a memory selecting region adjacent to the memory array region, a semiconductor gate electrode, a semiconductor channel connecting to the semiconductor gate electrode, a gate dielectric layer, a gate electrode layer, and channel layer. The gate electrode layer and the semiconductor channel are in the memory selecting region. The gate electrode layer and the semiconductor channel are separated from each other by the gate dielectric layer. The channel layer and the semiconductor gate electrode are in the memory array region. The channel layer and the semiconductor gate electrode are separated from each other by the gate dielectric layer.