3D NAND Memory String Structural Stability via Vertical Channel Design
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Solution Overview
Problem
The manufacturing of 3-D structured memory strings for NAND flash memory devices faces challenges in achieving high structural reliability due to differences in the manufacturing methods compared to 2-D structures, leading to potential structural instability.
Innovation Solution
The implementation of a semiconductor device design that includes a pipe channel layer, first and second vertical channel layers, a multi-layer with a charge trap layer, and an insulating barrier layer, along with alternating conductive and insulating layers, to enhance structural stability and manufacturing reliability. This design involves forming sacrificial layers, channel holes, and trench formation to create a stable 3-D memory string structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a 3-D structure is adopted to increase integration degree, then cell size reduction is achieved, but structural reliability deteriorates
Solution Approach 1:
The patent transitions from a 2-D memory string structure to a 3-D structure by forming vertical channel layers that extend in the depth direction through multiple conductive layers. This dimensional change enables increased integration density while maintaining structural integrity through careful design of the vertical architecture and surrounding insulation barriers.
Solution Approach 2:
The memory string is segmented into multiple functional components including pipe channel layers, vertical channel layers, charge trap layers, and insulation barriers that are formed in a systematic sequence. Each segment serves a specific function and contributes to the overall structural stability of the 3-D configuration.
2Ease of manufacture
If conventional 2-D manufacturing method is used, then manufacturing process is simple, but integration degree is limited
Solution Approach 1:
The manufacturing process employs preliminary actions by forming sacrificial layers before the main structure, creating templates that guide subsequent material deposition. The sacrificial layers are removed after defining the vertical channel structures, enabling precise 3-D formation while maintaining process control through sequential, well-defined steps.
Solution Approach 2:
Sacrificial layers serve as intermediary elements during manufacturing, temporarily occupying space to define the geometry of vertical channels. These intermediary structures facilitate the formation of complex 3-D architectures through standard deposition and etching processes, bridging the gap between simple 2-D manufacturing and complex 3-D structures.
3Area of moving object
If vertical channel layers are formed through multiple conductive layers, then integration degree increases, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple functions into unified structural elements. The vertical channel layers simultaneously serve as conductive pathways and structural supports, while the surrounding insulation barriers provide both electrical isolation and mechanical stability. This merging reduces the number of separate components and simplifies the overall manufacturing process despite the 3-D complexity.
Data Source
AI summary
A semiconductor device includes a pipe channel layer formed over a substrate, a first vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a bit line, a second vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a source line, a multi-layer comprising a charge trap layer and formed to surround the first vertical channel layer, the second vertical channel layer, and the pipe channel layer, an insulating barrier layer formed to surround the multi-layer, a plurality of first conductive layers formed between the pipe channel layer and the bit line, wherein the first vertical channel layer passes through the first conductive layers, and a plurality of second conductive layers formed between the pipe channel layer and the source line, wherein the second vertical layer passes through the second conductive layers.