3D NAND Memory Data Retention via Trap Charge Removal
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Solution Overview
Problem
Collectively patterned three-dimensional multilayer memory devices face issues with data retention characteristics due to traps at the channel interface, which degrade both during data erasing and writing operations.
Innovation Solution
The implementation of a nonvolatile semiconductor memory device with a multilayer structure comprising electrode films and insulating films, where a semiconductor pillar pierces through the structure, and a memory layer is positioned between the electrode films and the semiconductor pillar, with specific potential settings applied to improve data retention by performing 'strong erasing' and 'soft writing' or 'strong writing' and 'soft erasing' operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If collectively patterned three-dimensional multilayer memory is implemented, then memory capacity is increased and cost is suppressed, but data retention characteristics are degraded due to traps at the channel interface
Solution Approach 1:
The patent applies preliminary action by performing a first operation (strong erasing or soft erasing) before the second operation (writing). This preliminary operation removes charges from traps at shallow energy levels near the channel interface before data writing occurs, preventing the traps from degrading data retention characteristics during subsequent write and retain cycles
Solution Approach 2:
The patent changes the energy level parameter of charge removal by applying different potential settings in two sequential operations. The first operation targets shallow energy level traps near the channel interface, while the second operation writes data to the charge storage layer. This parameter differentiation allows selective removal of harmful charges without affecting stored data
2Reliability
If holes are injected from the channel side toward the charge storage layer during data erasing, then data erasing is achieved, but holes are captured in traps at the channel interface causing degraded data retention characteristics
Solution Approach 1:
The patent converts the harmful effect of hole capture in channel interface traps into a beneficial process. By intentionally applying a first erasing operation that generates hole injection, the patent systematically removes charges from shallow traps before data writing. This controlled harmful process becomes a useful preliminary step that improves overall data retention by clearing trap sites that would otherwise degrade stored data
3Reliability
If electrons are injected into the charge storage layer during data writing, then data writing is achieved, but electrons are captured in traps at the channel interface causing degraded data retention characteristics
Solution Approach 1:
The patent applies preliminary action by performing the first operation (strong erasing or soft erasing) to remove charges from channel interface traps before executing the second operation (writing). This preliminary charge removal prevents electrons injected during writing from being captured in pre-existing traps, thereby maintaining data retention characteristics
Solution Approach 2:
The patent establishes continuity of useful action by making the first operation (trap charge removal) an integral part of the writing process sequence. Rather than treating trap removal as a separate corrective measure, the patent incorporates it as a continuous preliminary step that ensures trap sites are cleared before each write operation, maintaining consistent data retention across multiple write cycles
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively removes charges captured at shallow energy levels near the channel interface, enhancing data retention characteristics in both erase and write operations, thereby improving the reliability and performance of the memory device.
Implementation Method 1
injection of a hole into the first memory layer and extraction of an electron from the first memory layer
Implementation Method 2
setting the first wiring at a first potential and setting the electrode film at a second potential
Data Source
AI summary
A nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; an inner insulating film provided between the memory layer and the semiconductor pillar; an outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In an erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential.