3D NAND Memory String Layout With Mid-Source Line for Higher Current
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Solution Overview
Problem
The challenge in 3D NAND memory devices is the reduction in current due to increased string length with more layers, which affects performance.
Innovation Solution
A 3D NAND structure is designed with a source line in the middle of the memory string, reducing string length and increasing current, while allowing high thermal budget processes without impacting top and bottom bit lines and CMOS wafer, and enabling improved RC performance through back-end-of-line processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more layers are stacked in 3D NAND memory devices to increase integration density, then the number of memory cells increases, but the string length increases and current decreases
Solution Approach 1:
The memory string is segmented into two separate strings (first memory string and second memory string) that are spaced apart by the source line. This segmentation divides the long vertical path into shorter segments, reducing the effective string length and improving current flow while maintaining high cell density through the stacked configuration.
Solution Approach 2:
The source line is positioned laterally between the first and second memory strings, creating a three-dimensional arrangement where the source line extends in the lateral direction rather than vertically. This dimensional reconfiguration allows the source line to serve both strings simultaneously while reducing the vertical string length.
2Ease of manufacture
If high thermal budget processes are used during fabrication to improve manufacturing, then manufacturing quality improves, but existing bit lines and CMOS wafer may be damaged
Solution Approach 1:
The source line is formed preliminarily before the bit lines and CMOS wafer are integrated. This preliminary formation allows subsequent high thermal budget processes to be applied to complete the source line and memory string structure without exposing the already-formed bit lines and CMOS devices to damaging temperatures.
Solution Approach 2:
The fabrication process is segmented into stages where different components are formed at different times. The source line and memory strings are formed in earlier stages that can tolerate high temperatures, while bit lines and CMOS integration occur in later stages with lower thermal budgets, protecting sensitive components.
3Reliability
If back-end-of-line processes are used to improve RC performance, then signal transmission improves, but process complexity increases
Solution Approach 1:
The source line formation is merged with the memory string structure formation in the back-end-of-line process. By combining these functions into a single integrated structure formed during later processing stages, the patent achieves improved RC performance without requiring separate additional process modules.
Data Source
AI summary
An integrated circuit structure includes a substrate, a first memory string, a source line, and a second memory string. The first memory string is over the substrate and comprises first memory cells stacked in a vertical direction. The source line laterally extends over the first memory string. The second memory string is over the source line and comprises second memory cells stacked in the vertical direction.