3D NAND Flash Memory Integration with NOR Flash on CMOS Die
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SSDs using a combination of SLC and 3D TLC NAND flash memory reduce storage density and increase costs, while also failing to meet satisfactory read/write performance requirements.
Innovation Solution
Integrating multiple 3D triple-level cell (TLC) NAND flash memories with at least one NOR Flash memory on a CMOS die, connected via an Open NAND Flash Interface (ONFI), with the NOR Flash memory disposed in unused areas to enhance storage capacity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a combinational structure of SLC NAND flash and 3D TLC NAND flash is used, then read/write performance is improved, but storage density is reduced and cost increases
Solution Approach 1:
The patent combines SLC NAND flash and 3D TLC NAND flash into a single integrated package with a unified controller, allowing them to work together as a cohesive storage system. This merging enables the system to achieve both high performance (from SLC) and high storage density (from 3D TLC) simultaneously, rather than treating them as separate competing solutions.
Solution Approach 2:
The unified controller manages both SLC and 3D TLC NAND flash memories, making it a multi-functional control system that can handle different types of flash memory with different characteristics. This universal controller optimizes data placement and access patterns to leverage the speed advantages of SLC for hot data while utilizing the high density of 3D TLC for cold data, thereby achieving both performance and density goals.
2Speed
If a combinational structure of SLC NAND flash and 3D TLC NAND flash is used, then read/write performance is improved, but manufacturing cost increases
Solution Approach 1:
By integrating SLC and 3D TLC NAND flash into a single package with a unified controller, the patent reduces the need for separate control logic and interface circuits that would be required if the two memory types were implemented separately. This consolidation simplifies the overall system architecture and reduces component count, leading to lower manufacturing costs despite using multiple memory types.
3Speed
If SLC NAND flash is used for hot data, then read/write performance is improved, but storage density is reduced
Solution Approach 1:
The patent segments the storage system into two distinct parts: SLC NAND flash for storing hot data that requires frequent access, and 3D TLC NAND flash for storing cold data that prioritizes density. This segmentation allows each memory type to be optimized for its specific function, with the unified controller intelligently managing data placement between the two segments based on access patterns and performance requirements.
Solution Approach 2:
Different regions of the storage system are assigned different qualities: the SLC portion provides high-speed access characteristics for performance-critical operations, while the 3D TLC portion provides high-density storage characteristics for capacity-critical operations. This local quality differentiation allows the system to optimize both performance and density in their respective domains simultaneously.
Data Source
AI summary
An integration method for a 3D NAND flash memory device includes disposing a plurality of 3D triple-level cell (TLC) NAND flash memories on a CMOS die; disposing at least a NOR Flash memory on the CMOS die of the 3D NAND flash memory device; and connecting the at least a NOR Flash memory to an Open NAND Flash Interface (ONFI) of the 3D NAND flash memory device; wherein the at least a NOR Flash memory is disposed on an unused area of the CMOS die.