3D NAND Memory Layout With Over-Array Control Logic

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Solution Overview

Problem

Microelectronic device designers face challenges in increasing memory density and performance while minimizing device size, as processing conditions and control logic device configurations limit the reduction of feature dimensions and improvement of memory device performance in conventional 3D NAND Flash memory devices.

Innovation Solution

The solution involves forming a microelectronic device with a memory array region and a control logic region, where the memory array region includes vertically alternating conductive and insulating structures, and an additional control logic region is positioned over the memory array to enhance control operations, allowing for improved miniaturization and performance by reducing the horizontal footprint and threshold switching voltage requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If processing conditions (temperatures, pressures, materials) are optimized for memory array formation, then memory array quality is improved, but control logic device configurations are limited

Engineering Contradiction:

Improvememory array qualityVSAvoidcontrol logic device configurations

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The device is divided into two separate structures: a first microelectronic device structure containing the memory array region, and a second microelectronic device structure containing the additional control logic region. This segmentation allows each structure to be optimized independently for its specific processing requirements, resolving the contradiction between memory array quality and control logic device configuration flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate connection structures (interconnects, vias, routing structures) that bridge the memory array region and the additional control logic region. These intermediaries enable electrical communication between the two separately optimized structures, allowing them to function as an integrated system while maintaining independent optimization.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If control logic devices are increased in quantity and complexity, then control operations are enhanced, but horizontal footprint increases

Engineering Contradiction:

Improvecontrol operationsVSAvoidhorizontal footprint

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical architecture. The additional control logic region is positioned vertically over the memory array region, utilizing the vertical dimension to accommodate more control logic devices without increasing the horizontal footprint. This dimensional transition enables enhanced control operations while maintaining compact device area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If feature dimensions are reduced, then memory density is increased, but processing conditions become more constrained

Engineering Contradiction:

Improvememory densityVSAvoidprocessing conditions

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

By segmenting the device into separate first and second microelectronic device structures, each with their own processing optimization, the patent enables reduced feature dimensions in the memory array region (increasing density) without constraining the processing conditions for the control logic region. Each structure can be manufactured with feature dimensions optimized for its specific functional requirements.

Inventive Principle:

Principle #1Segmentation

4Device complexity

If conventional base control logic structure is used, then device simplicity is maintained, but memory device performance is limited

Engineering Contradiction:

Improvedevice simplicityVSAvoidmemory device performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent merges a conventional base control logic structure with an additional control logic region to create a hybrid architecture. The first control logic region provides foundational control operations, while the second control logic region adds enhanced functionality and performance. This merging maintains reasonable device complexity while significantly improving memory device performance through the additional control capabilities.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12199070B23D NAND memory device devices and related electronic systems

Publication Date: 2025.01.14 LODESTAR LICENSING GROUP LLC

AI summary

A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.