3D NAND Channel Structure With Self-Aligned Overlapping Holes
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Solution Overview
Problem
The manufacturing of advanced 3D NAND memory devices faces challenges such as poly-silicon based inter-deck plugs suffering from ONO dielectric residual issues and single channel formation technology narrowing the process window, leading to electrical performance issues like data retention and read/erase speed problems.
Innovation Solution
A structure and method for forming 3D NAND memory devices involving a substrate with alternating stack layers, channel holes, and a sacrificial layer, where a self-aligned etch process forms overlapping channel holes and a functional layer to improve channel alignment and reduce process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If poly-silicon based inter-deck plugs are used to connect decks, then electrical connection between decks is achieved, but ONO dielectric residual issues occur causing data retention and read/erase speed problems
Solution Approach 1:
The patent removes the poly-silicon inter-deck plug structure that causes ONO dielectric residual issues. Instead of using plugs to connect decks, the invention uses a through-channel structure that extends continuously through multiple decks, eliminating the need for inter-deck plugs and the associated dielectric residual problems that harm electrical performance
Solution Approach 2:
The patent segments the memory device into multiple decks connected through a continuous channel structure, where each deck is separated by block layers but interconnected through the through-channel. This segmentation approach maintains electrical connection reliability while avoiding the harmful effects of traditional plug-based connections
2Ease of manufacture
If single channel formation technology is used to simplify the process, then manufacturing steps are reduced, but channel alignment precision and process window are narrowed
Solution Approach 1:
The patent forms block layers between decks before forming the through-channel structure. These pre-formed block layers serve as alignment references and etch stop layers, enabling precise channel formation through multiple decks while maintaining a simplified single-channel process. The preliminary placement of block layers ensures that subsequent channel etching achieves high alignment precision without complicating the overall manufacturing process
Solution Approach 2:
The block layers act as intermediary structures that facilitate the single channel formation process. They provide physical references for alignment and control the etching process, enabling precise through-channel formation while keeping the manufacturing process simple and avoiding the need for complex multi-step alignment procedures
3Quantity of substance
If more oxide/metal layers are stacked to increase capacity, then storage density increases, but channel hole etching becomes exponentially slower and more difficult to control
Solution Approach 1:
The patent segments the deep channel formation into multiple shallower etching steps by introducing block layers between decks. Instead of etching one extremely deep channel through all layers, the process forms channels through individual decks separated by block layers, dramatically increasing etching speed and process control while achieving the same total storage capacity through stacked deck architecture
Solution Approach 2:
The block layers are pre-formed between decks before channel etching. These preliminary structures serve as etch stop layers that define the depth of each etching step, enabling the formation of multiple decks with high capacity while maintaining fast and controllable etching speeds by breaking down the single deep etch into multiple shallow etches
Data Source
AI summary
A method of forming a structure of 3D NAND memory device, including steps of forming a first stack layer on a substrate, forming a first channel hole extending through the first stack layer, forming a block layer on a surface of the first stack layer and the first channel hole, forming a sacrificial layer in the first channel hole, forming a second stack layer on the first stack layer and the sacrificial layer, performing a first etch process to form a second channel hole extending through the second stack layer and at least partially overlapping the first channel hole and to remove the sacrificial layer in the first channel hole, removing the block layer exposed from the second channel hole, and forming a function layer on a surface of the first channel hole and the second channel hole.