3D-NAND Stack Oxide Density Profiling for Charge Trap Control
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Solution Overview
Problem
Current 3D-NAND flash memory devices face challenges in increasing memory density while maintaining device size, as charge trapping in inter-poly dielectric materials degrades cell program-erase cycling and alters threshold voltage, requiring complex and costly fabrication processes to increase floating gate height.
Innovation Solution
A semiconductor fabrication process that forms floating gates with a height equal to adjacent control gates using an oxide material with varying densities, allowing for selective etching to control the height and profile of control gate recesses without adding complex steps, thereby minimizing charge trap and maintaining critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional oxide material is used as dielectric material in 3D-NAND flash memory, then the fabrication process is simpler, but charge trapping occurs in the inter-poly dielectric material which degrades cell program-erase cycling and alters threshold voltage
Solution Approach 1:
The oxide material is segmented into multiple layers with different densities (first oxide layer with first density, second oxide layer with second density). This segmentation allows selective etching of specific layers while preserving others, enabling precise control over control gate recess formation without requiring complex multi-step fabrication processes. The differentiated density structure inherently provides the necessary selectivity that would otherwise require complex process control.
Solution Approach 2:
Different regions of the oxide material are given different densities to serve different functions. The first oxide layer with higher density provides better charge blocking properties, while the second oxide layer with lower density is selectively removed to form control gate recesses. This local quality differentiation resolves the contradiction by providing both reliability (through high-density charge blocking regions) and process simplicity (through inherent etch selectivity of density-differentiated regions).
2Reliability
If floating gate height is increased to improve channel conductance modulation, then reliability is enhanced, but critical dimensions are compromised and process complexity increases
Solution Approach 1:
The oxide material is pre-structured with differentiated density layers before control gate formation. This preliminary action of creating density-varied oxide layers enables subsequent selective etching to precisely define control gate recess dimensions. The pre-established density differentiation acts as a built-in template that guides the etching process, maintaining critical dimension control while allowing floating gate height to be optimized for reliability.
Solution Approach 2:
The density parameter of the oxide material is changed across different layers to achieve functional differentiation. By varying the density parameter, the invention creates regions with different etch rates, enabling precise control over the morphology and dimensions of control gate recesses. This parameter change approach allows floating gate height to be increased for better reliability without compromising critical dimension precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased floating gate height without compromising critical dimensions or process complexity, enhancing channel conductance modulation and reliability while reducing charge trapping, thus improving the performance and reliability of 3D-NAND flash memory devices.
Implementation Method 1
A semiconductor fabrication process that forms floating gates with a height equal to adjacent control gates using an oxide material with varying densities, allowing for selective etching to control the height and profile of control gate recesses
Data Source
AI summary
Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.


