3D NAND Page Register Selective Reset for Power Reduction
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Solution Overview
Problem
The reset process of page registers in 3D NAND memory devices increases peak power, total power, and power noise due to unnecessary resetting of all page registers during write operations, even when only some planes require data changes.
Innovation Solution
A method and system for a 3D memory device that allows selective resetting of page registers based on the address of the program command, where only the page register corresponding to the addressed plane is reset, maintaining the status of other page registers unchanged.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all page registers are reset during write operations, then data integrity is ensured, but peak power and total power consumption increase
Solution Approach 1:
The patent segments the page register reset operation by plane. Instead of resetting all page registers across all planes simultaneously, the controller identifies the specific plane addressed by the write command and resets only the page register associated with that plane. This segmentation allows data integrity to be maintained for the targeted plane while avoiding unnecessary power consumption from resetting other planes' registers.
Solution Approach 2:
The patent applies local quality by making the reset operation localized to the specific plane being written. The controller determines which plane is targeted by the write command and applies the reset operation only to that plane's page register, rather than uniformly resetting all page registers. This localized approach ensures data integrity where needed while reducing overall power consumption.
2Reliability
If all page registers are reset during write operations, then data consistency is maintained, but power noise increases
Solution Approach 1:
The patent segments the reset operation to affect only the page register of the targeted plane. By dividing the reset operation into plane-specific instances rather than a global simultaneous reset, the patent reduces the number of registers being reset at any given time, thereby reducing power noise while maintaining data consistency for the relevant plane.
Solution Approach 2:
The patent applies local quality by confining the reset operation to the specific plane being written. The controller identifies the targeted plane and resets only that plane's page register, creating a localized reset effect that maintains data consistency where needed while minimizing power noise generation from other parts of the system.
3Use of energy by stationary object
If selective page register reset is implemented, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by having the controller determine the targeted plane before executing the reset operation. The controller extracts plane identification information from the write command address, identifies which plane is being written, and then proceeds to reset only that plane's page register. This preliminary identification step enables selective resetting without requiring complex additional hardware, as the plane identification is derived from existing address information.
Data Source
AI summary
A method for programming a memory device having a plurality of planes is provided. Program commands and addresses are received. Each of the addresses associated with one of the program commands. A first plane of the plurality of planes are determined according to a first address of the addresses. A page register of the first plane is reset. A second plane of the plurality of planes is determined according to a second address of the addresses. A page register of the second plane is reset.