3D NAND Memory Control Circuit for Parallel Low-Power Reads
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Solution Overview
Problem
Existing semiconductor devices struggle to efficiently execute complex logical operations and handle large volumes of data at low power consumption, particularly in NAND flash memories with three-dimensionally stacked memory cells.
Innovation Solution
The semiconductor device incorporates a control circuit that applies specific voltages to select transistors and memory cells in series to perform logical operations, allowing simultaneous conductance of multiple NAND strings and enabling efficient read operations based on threshold voltage values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple NAND strings are operated simultaneously to increase processing throughput, then productivity is improved, but power consumption increases due to simultaneous voltage application across multiple strings
Solution Approach 1:
The bit line is divided into multiple independent bit line groups (first bit line group and second bit line group), each capable of independent voltage application. This segmentation allows selective operation of different string sets, enabling parallel processing while controlling power consumption by activating only the necessary groups for each operation.
Solution Approach 2:
The patent implements dynamic voltage control where different voltage levels are applied to different bit line groups based on operational requirements. The control circuit dynamically selects which bit line groups receive voltage during read operations, adjusting power distribution in real-time to match the actual processing needs and minimize unnecessary power consumption.
2Quantity of substance
If three-dimensionally stacked memory cells are used to increase storage capacity, then the quantity of data storage is improved, but device complexity increases due to the need for multiple select transistors and complex voltage control
Solution Approach 1:
The control circuit is designed with multi-functionality to handle complex voltage control requirements through a unified control mechanism. It can selectively apply different voltages to different bit line groups and manage multiple select transistor operations through a single integrated control structure, reducing the perceived complexity while maintaining the capability to support 3D stacked memory operations.
Solution Approach 2:
The control circuit divides the memory array into multiple independently controllable regions (bit line groups), each with its own select transistor. This segmentation allows the complex 3D memory structure to be managed through modular control units, making the overall system more manageable despite the increased storage capacity.
3Loss of energy
If selective voltage application is implemented to reduce power consumption, then energy efficiency is improved, but the difficulty of detecting and measuring increases due to differential voltage levels
Solution Approach 1:
The control circuit applies the same voltage level to all select transistors within a given bit line group, creating equipotential conditions for selected strings. This uniform voltage application simplifies the detection and measurement processes by ensuring consistent electrical conditions across all active memory cells, making it easier to read data while maintaining energy efficiency through selective group operation.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first bit line, strings, and a first control circuit. The strings are coupled to the first bit line. Each string includes a select transistor and memory cells, which are coupled in series. The first control circuit is configured to execute a logical operation. In the logical operation, the first control circuit is configured to execute a read operation to apply a first voltage to the select transistors of at least two strings of the strings, to apply a second voltage lower than the first voltage to the select transistor of a string other than the at least two strings, to apply a third voltage to at least two memory cells of the memory cells of each string, and to apply a fourth voltage higher than the third voltage to the memory cells other than the at least two memory cells.