3D NAND Memory Stacking for Peripheral Circuit Separation
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Solution Overview
Problem
Planar memory cells face density limitations and scaling challenges as feature sizes approach a lower limit, leading to increased costs and complexity in fabrication, while traditional CMOS technology scaling is infeasible due to high voltage requirements and leakage issues.
Innovation Solution
The 3D memory architecture separates memory cell arrays and peripheral circuits into different vertical planes, using hybrid or transfer bonding to stack these components independently, allowing for parallel fabrication and reducing planar chip size by integrating interconnects with different thermal budgets and voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional stacked architecture. Multiple semiconductor structures are bonded vertically to form stacked memory devices, enabling memory density improvement without proportionally increasing fabrication complexity. The stacking approach utilizes the vertical dimension to achieve higher density while maintaining separate, optimized fabrication processes for each layer.
Solution Approach 2:
The memory device is divided into multiple independent semiconductor structures that can be fabricated separately and then bonded together. Each semiconductor structure contains memory cells and peripheral circuits as distinct segments, allowing independent optimization and parallel fabrication. This segmentation reduces the complexity of fabricating entirely new high-density planar structures.
2Length of moving object
If traditional CMOS technology is scaled, then device size is reduced, but high voltage requirements and leakage issues make scaling infeasible
Solution Approach 1:
The patent separates memory cell arrays and peripheral circuits into different semiconductor structures that are bonded together. This segmentation allows different voltage domains to be isolated in separate structures, enabling independent voltage optimization. Memory cells can operate at higher voltages while peripheral circuits operate at lower voltages, reducing leakage without compromising functionality.
Solution Approach 2:
Different semiconductor structures are optimized with local quality variations - memory cell regions use structures and materials suited for high-voltage operation and high density, while peripheral circuit regions use structures optimized for low-voltage operation and low leakage. This local optimization resolves the contradiction between size reduction and voltage control reliability.
3Area of stationary object
If memory cell arrays and peripheral circuits are integrated in the same planar space, then chip area is utilized efficiently, but optimizing layout becomes challenging and increases fabrication complexity
Solution Approach 1:
The patent divides the memory device into separate semiconductor structures - one containing memory cell arrays and others containing peripheral circuits. These segmented structures are fabricated independently with optimized layouts for their specific functions, then bonded together. This eliminates the complexity of integrating conflicting layout requirements in a single planar space while achieving efficient area utilization through vertical stacking.
Solution Approach 2:
By moving from planar integration to three-dimensional stacking, the patent resolves the layout optimization challenge. Memory cell arrays and peripheral circuits are arranged in different vertical layers rather than competing for the same planar space. Each layer can be independently optimized for its specific function, simplifying the manufacturing process while efficiently utilizing the total chip volume.
Data Source
AI summary
A method for forming a three-dimensional (3D) memory device is disclosed. An array of NAND memory strings is formed on a first substrate. A first semiconductor layer is formed above the array of NAND memory strings. The first semiconductor layer includes single crystalline silicon. A first transistor is formed on the first semiconductor layer. A second semiconductor layer is formed above the first transistor. The second semiconductor layer includes single crystalline silicon. A second transistor is formed on the second semiconductor layer.