3D NAND Memory Pillar Array with Sacrificial Layer Support

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Solution Overview

Problem

In three-dimensional nonvolatile memory devices, existing manufacturing methods struggle to maintain the integrity and density of memory cells due to issues with word line separation and pillar structure stability, leading to potential collapse and reduced memory cell density.

Innovation Solution

The semiconductor storage device employs a configuration where memory cells are arrayed on both sides of pillars with alternating insulating and conductive layers, using sacrificial layers to support the structure and maintain periodicity, allowing for higher density without collapsing, and forming memory holes before insulating layers to prevent deformation and enhance electrical characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are densely packed in three-dimensional nonvolatile memory, then memory cell density increases, but word lines may collapse due to insufficient separation

Engineering Contradiction:
Improvememory cell densityVSAvoidword line stability
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

Sacrificial layers are formed in advance between word lines during the stacking process to provide temporary support and separation. These sacrificial layers are deposited before the final memory structure is complete, allowing word lines to be separated and supported during manufacturing. After the structure is formed, the sacrificial layers are removed, leaving cleanly separated word lines that maintain their positions without collapse, thus enabling high density while preventing structural failure.

Inventive Principle:
Principle #10Preliminary action

2Stability of the object's composition

If separation is performed finely to prevent collapse, then word line stability is maintained, but manufacturing complexity increases

Engineering Contradiction:
Improveword line separationVSAvoidmanufacturing process complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The manufacturing process is segmented into distinct stages: first forming the stack structure with alternating insulating and conductive layers, then selectively removing sacrificial layers to create separations, and finally forming the memory holes. This segmentation allows each step to be optimized independently, achieving fine separation without requiring the entire process to be overly complex. The sacrificial layers act as temporary dividers that simplify the overall manufacturing approach.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If memory holes are formed before insulating layers, then structural deformation is prevented, but process sequence complexity increases

Engineering Contradiction:
Improvememory hole shape accuracyVSAvoidprocess sequence complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Memory holes are formed in advance through the stack structure before the final insulating layers are deposited. This preliminary formation of memory holes establishes the correct positions and shapes early in the process, preventing deformation that would occur if holes were formed later when additional layers were added. The subsequent insulating layers are then deposited conformally around the pre-formed holes, maintaining their shapes while providing the necessary structural support and electrical isolation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11049871B2Semiconductor storage device and manufacturing method of semiconductor storage device
Publication Date: 2021.06.29 KIOXIA CORP
  • US11049871B2 patent drawing
  • US11049871B2 patent drawing
  • US11049871B2 patent drawing

AI summary

A semiconductor storage device of an embodiment includes a plurality of pillars extending in a predetermined direction, a plurality of first memory cells arrayed on a side surface on one side of each of the pillars along an extending direction of the pillars, a plurality of second memory cells arrayed on a side surface of on another side each of the pillars along the extending direction of the pillars, a plurality of first and second word lines arrayed in the extending direction of the pillars, and respectively connected to the first and second memory cells, and in a cell array in which the plurality of pillars is disposed, the plurality of pillars are periodically arrayed without interruption in a lead-out direction of the first word lines and the second word lines.