3D NAND Memory Pillar Structure for Consistent Current Flow
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Solution Overview
Problem
Existing three-dimensional NAND flash memory architectures face challenges in maintaining consistent current flow and reducing voltage loss due to defects and dimensional offsets in vertical NAND strings, which affect the performance and reliability of the memory devices.
Innovation Solution
The solution involves fabricating a three-dimensional NAND flash memory structure with a semiconductor pillar that serves as a common body for memory cells, using a monolithic pillar of semiconductor material to minimize defects and reduce voltage loss, and incorporating field effect transistors (FETs) with charge storage mechanisms between the control gate and channel, ensuring consistent current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical NAND strings are used in three-dimensional memory architecture, then storage density is improved, but voltage loss and performance variability worsen due to defects and dimensional offsets
Solution Approach 1:
The vertical NAND string is segmented into multiple memory cells with individual control gates, allowing independent control and compensation of voltage loss in different segments. This segmentation enables selective optimization of voltage distribution along the vertical channel while maintaining high storage density.
Solution Approach 2:
Different regions of the vertical NAND string are equipped with different control gate structures and materials optimized for their specific functions. The control gates are positioned at different heights and have varying dimensions to compensate for local voltage drops and defects, ensuring uniform performance throughout the high-density vertical structure.
2Adaptability or versatility
If control gates are positioned at different heights in vertical NAND strings, then access flexibility is improved, but manufacturing precision requirements worsen
Solution Approach 1:
Control gates are nested within the vertical NAND string structure at different height levels, with each control gate embedded in its own insulating layer. This nested arrangement provides precise positional control during manufacturing while enabling flexible access to different memory cell regions through selective gate activation.
Solution Approach 2:
The control gates are pre-positioned at specific heights during the fabrication process, with their locations predetermined by the vertical NAND string architecture design. This preliminary positioning establishes the flexible access capability before device operation, while the manufacturing process is optimized to achieve the required positioning precision.
3Quantity of substance
If three-dimensional stacked memory cells are implemented, then storage capacity is improved, but defect impact on current flow worsens
Solution Approach 1:
The control gates serve multiple functions: they control current flow through their respective memory cells, compensate for voltage loss, and provide redundancy against defects. This multi-functionality allows the three-dimensional stacked structure to maintain high storage capacity while mitigating the impact of defects through alternative current paths and voltage compensation mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and performance of three-dimensional NAND flash memory by reducing defects' impact on current flow and minimizing voltage loss, thereby improving the overall efficiency and stability of the memory device.
Implementation Method 1
field effect transistors (FETs) with charge storage mechanisms between the control gate and channel
Implementation Method 2
flash memory which stores charge in a charge storage region of a memory cell
Data Source
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AI summary
A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.