3D NAND Pillar Grid Rotation for Select Line Width
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional memory structures face challenges in increasing bit density while minimizing the negative impacts such as increased power consumption and slowed device operation due to the need for deep etches and wider spacing between pillars, which complicates the fabrication process and leads to read/write disturbances.
Innovation Solution
The use of rotated and parallelogram grid arrangements for pillars in 3D memory devices, allowing for wider string select lines and ground select lines, which reduces the number of select lines, increases bit line density, and decreases unit cell capacitance, thereby improving data rate and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pillars are spaced closer together to increase bit density, then storage capacity increases, but fabrication difficulty increases due to deep etches and process window constraints
Solution Approach 1:
The patent transitions from conventional 2D planar memory architecture to a 3D vertical architecture where memory cells are stacked in multiple layers along the vertical dimension. This allows bit density to increase by utilizing the third dimension (stack height) rather than simply reducing lateral pillar spacing, thereby avoiding the fabrication difficulties associated with deep etches and narrow process windows.
2Adaptability or versatility
If the number of select lines is increased to address more pillars, then pillar addressing capability improves, but device complexity and power consumption increase
Solution Approach 1:
The patent introduces a vertical stacking dimension where multiple memory cell layers share common bit lines and select lines. By organizing memory cells in vertical stacks rather than lateral arrays, the architecture reduces the number of select lines needed while maintaining the ability to address individual pillars through the vertical dimension (layer selection combined with pillar selection within each layer).
Solution Approach 2:
The patent makes select lines multi-functional by having them serve multiple pillars across different layers. A single select line can control access to multiple pillars in a vertical stack, and bit lines similarly serve multiple memory cell layers, thereby reducing the total number of conductors needed while maintaining full addressing capability.
3Ease of manufacture
If pillar spacing is increased to simplify fabrication, then manufacturing ease improves, but bit line density and data rate decrease
Solution Approach 1:
The patent compensates for reduced bit line density (caused by larger pillar spacing) by utilizing the vertical dimension with multiple stacked memory cell layers. The increased vertical capacity offsets the lateral spacing requirements, allowing larger pillar spacing for fabrication ease while maintaining high data rates through parallel access to multiple layers.
4Quantity of substance
If more string select lines are used to access more memory cells, then memory capacity increases, but unit cell capacitance and power consumption increase
Solution Approach 1:
The patent makes string select lines multi-functional by having each select line control multiple memory cell layers vertically stacked beneath it. A single select line activation can access multiple pillars across different layers, thereby increasing memory capacity without proportionally increasing the number of select lines, thus limiting the increase in unit cell capacitance and power consumption.
Data Source
AI summary
Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into word lines. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the layers. String select lines run above the conductive layers and define select gates of the pillars. Bit lines run above the SSLs. The pillars are arranged on a regular grid having a unit cell area α, and adjacent ones of the string select lines have respective widths in the bit line direction which are at least as large as (α/pBL). Ground select lines run below the conductive layers and define ground select gates of the pillars. The ground select lines, too, may have respective widths in the bit line direction which are at least as large as (α/pBL).