3D NAND Pillar Patterning With LELE Stripe Layout and Buttress Support

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing 3D NAND memory device fabrication faces challenges in achieving uniformity and evenness of patterned feature sizes and shapes on the hard mask due to limitations of single exposure lithography techniques, particularly in forming memory pillars with varying dimensions.

Innovation Solution

Employing a Litho-Etch-Litho-Etch (LELE) technique to create overlapping stripes patterns on the hard mask layer, forming square peripheral shapes aligned in columns and rows, and incorporating supporting buttress pillars (SBT) at the memory pillar edges to enhance structural support during etching processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If single exposure lithography technique is used, then the fabrication process is simple, but the uniformity and evenness of patterned feature size and shape deteriorates

Engineering Contradiction:

Improvefabrication process simplicityVSAvoiduniformity and evenness of patterned feature size and shape

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent divides the single exposure lithography process into two separate exposure steps (first exposure and second exposure) with different pitch values. The first exposure creates patterns at a first pitch, and the second exposure creates patterns at a second pitch, allowing each exposure to be optimized independently for uniformity and evenness while maintaining overall process feasibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension by performing exposures at different times (first exposure then second exposure) rather than simultaneously. This allows the fabrication process to achieve high uniformity and evenness across features of different sizes by separating the patterning events, effectively adding a time dimension to the fabrication process.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If feature density is increased in the support region, then hard mask patterning uniformity is improved, but the device complexity increases

Engineering Contradiction:

Improvehard mask patterning uniformityVSAvoiddevice complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies different pitch values to different regions of the hard mask layer. The core region receives patterning at a first pitch while the support region receives patterning at a second pitch, allowing each region to have optimized feature density for its specific function without increasing overall device complexity.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS12550738B2Patterning of 3D NAND pillars and flying buttress supports with two stripe technique

Publication Date: 2026.02.10 MICRON TECHNOLOGY INC

AI summary

A three-dimensional (3D) memory device including a stack of alternating supporting lattice layers and dielectric layers on a substrate, a plurality of memory pillars vertically penetrating the stack, each of the plurality of memory pillars including a plurality of vertically connected replacement gate (RG) memory cells that correspond to the supporting lattice layers, each of the memory pillars having a first square peripheral shape in a horizontal plane parallel to the supporting lattice layers, and a plurality of supporting buttress (SBT) pillars exclusive of any memory cells that are located at outside ends of the plurality of memory pillars and that vertically penetrate the stack, wherein the plurality of memory pillars and the plurality of SBT pillars are laterally connected by the supporting lattice layers.