3D NAND Pillar Structure With Local Thickness Reinforcement
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Solution Overview
Problem
The challenge in improving the reliability and manufacturing yield of multilayer three-dimensional NAND flash memory devices is evident, as existing technologies face difficulties in enhancing the structural integrity and consistency of semiconductor memory cells, leading to inefficiencies in data storage and processing.
Innovation Solution
The semiconductor memory device incorporates a unique configuration with alternately stacked insulating and conductive layers, a pillar structure comprising a semiconductor layer and a charge storage layer, and specific film thickness variations to enhance the reliability and manufacturing yield by optimizing the film thickness of the semiconductor layer in critical regions, thereby improving the characteristics of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the film thickness of the semiconductor layer is reduced to increase storage capacity, then the density of memory cells increases, but the reliability and manufacturing yield deteriorate due to discontinuity and structural instability
Solution Approach 1:
The patent applies local quality by creating a connecting part with increased film thickness in the semiconductor layer where it interfaces with the third insulating layer. This localized thickening provides structural support and ensures continuity at the critical interface between stacked bodies, while the rest of the semiconductor layer maintains reduced thickness to maximize storage capacity. The connecting part acts as a reinforcement zone that locally enhances reliability without sacrificing overall density.
Solution Approach 2:
The patent introduces a vertical dimension variation in the semiconductor layer thickness, creating a three-dimensional structure with different thickness zones. The connecting part extends vertically with greater thickness to bridge the interface between stacked bodies, while the main body of the semiconductor layer maintains uniform reduced thickness. This dimensional variation allows simultaneous achievement of high density and structural integrity.
2Quantity of substance
If the film thickness of the semiconductor layer is reduced to improve integration density, then the number of memory cells per unit area increases, but the manufacturing precision and uniformity deteriorate
Solution Approach 1:
The patent implements local quality by differentiating the semiconductor layer into two distinct thickness regions: a connecting part with increased thickness for structural stability and continuity, and a main body with reduced thickness for high integration density. This localized thickness variation allows the manufacturing process to focus precision requirements on the critical connecting interfaces while maintaining uniformity in the bulk storage regions.
Solution Approach 2:
The patent applies preliminary action by pre-establishing the connecting parts with increased film thickness at the interfaces between stacked bodies before final memory cell formation. This preliminary structural reinforcement ensures that subsequent manufacturing processes can proceed with higher precision, as the thickened connecting parts provide a stable foundation and reference structure for aligning and forming the thin semiconductor layers in the main body.
3Quantity of substance
If the semiconductor layer is made thinner to increase cell density, then the storage capacity per unit volume increases, but the structural integrity and continuity deteriorate
Solution Approach 1:
The patent applies local quality by creating a connecting part with increased film thickness specifically at the interfaces between stacked bodies, where structural integrity is most critical. This localized thickening provides mechanical support and ensures continuity of the semiconductor layer across multiple stacked bodies, while the main body of the semiconductor layer maintains reduced thickness to maximize storage capacity. The connecting part acts as a structural bridge that locally reinforces integrity without compromising overall density.
Solution Approach 2:
The patent introduces vertical dimensionality variation in the semiconductor layer, creating a multi-level thickness structure. The connecting parts extend vertically with greater thickness to span the interfaces between stacked bodies, providing structural continuity across layers. The main body maintains uniform reduced thickness optimized for storage. This three-dimensional thickness modulation allows simultaneous achievement of high storage capacity and structural integrity.
Data Source
AI summary
A semiconductor memory device includes a semiconductor substrate, a first stacked body including a plurality of first insulating layers and a plurality of first conductive layers alternately stacked in a first direction intersecting a surface of the semiconductor substrate, a second stacked body including a plurality of second insulating layers and a plurality of second conductive layers alternately stacked in the first direction of the first stacked body, a third insulating layer arranged between the first stacked body and the second stacked body, and a pillar penetrating the first stacked body, the third insulating layer, and the second stacked body, the pillar comprising a semiconductor layer extending in the first direction and a charge storage layer extending in the first direction and arranged between the plurality of first conductive layers and the semiconductor layer and between the plurality of second conductive layers and the semiconductor layer.